Display apparatus and display panel
AssigneeSharp Display Technology Corporation
InventorHidetoshi Nakagawa
Life of this patent
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Abstract
A display apparatus includes: a display panel including a display region, a first peripheral region, and a second peripheral region; and a circuit substrate. The display panel includes a gate drive circuit, n number of clock main lines, an outer main line and an inner main line, and a plurality of branch wiring lines. The first peripheral region includes a plurality of unit regions. The plurality of unit regions includes a first unit region and a second unit region. A resistance value of the at least one branch wiring line between the inner main line and the outer main line in the first unit region is smaller than a resistance value of the at least one branch wiring line between the inner main line and the outer main line in the second unit region.
Claims19
A display apparatus including a plurality of pixels arrayed in a matrix including a plurality of pixel rows and a plurality of pixel columns, the display apparatus comprising:
- a display panel including a display region defined by the plurality of pixels, a first peripheral region adjacent to the display region in a row direction, and a second peripheral region adjacent to the display region in a column direction;
- and
- a circuit substrate connected to a terminal portion provided in the second peripheral region of the display panel,
- wherein the display panel includes
- a gate drive circuit provided in the first peripheral region, the gate drive circuit including a shift register, the shift register including a plurality of stages individually corresponding to the plurality of pixel rows,
- n number of clock main lines provided in the first peripheral region, where n is an integer being equal to or larger than 2, each of the n number of clock main lines extending in the column direction, the n number of clock main lines being configured to supply n number of types of clock signals having different phases from one another to the plurality of stages included in the shift register,
- an outer main line and an inner main line provided in the first peripheral region, each of the outer main line and the inner main line extending in the column direction, and the outer main line and the inner main line being configured to supply a common signal to the plurality of stages included in the shift register, and
- a plurality of branch wiring lines provided in the first peripheral region, each of the plurality of branch wiring lines electrically connecting the outer main line and the inner main line,
- the circuit substrate includes a control circuit configured to supply a control signal to the gate drive circuit,
- the first peripheral region includes a plurality of unit regions arrayed in the column direction, the plurality of unit regions individually corresponding to the n number of stages included in the shift register, the n number of stages being configured to be supplied with the n number of types of clock signals having the different phases from one another from the n number of clock main lines,
- the plurality of branch wiring lines include at least one branch wiring line for each unit region, and
- the plurality of unit regions includes a first unit region and a second unit region, the first unit region being disposed closer to the terminal portion than the second unit region, a resistance value of the at least one branch wiring line between the inner main line and the outer main line in the first unit region being smaller than a resistance value of the at least one branch wiring line between the inner main line and the outer main line in the second unit region.
A display panel including a plurality of pixels arrayed in a matrix including a plurality of pixel rows and a plurality of pixel columns, a display region defined by the plurality of pixels, a first peripheral region adjacent to the display region in a row direction, and a second peripheral region adjacent to the display region in a column direction, the display panel comprising:
- a gate drive circuit provided in the first peripheral region, the gate drive circuit including a shift register, the shift register including a plurality of stages individually corresponding to the plurality of pixel rows;
- n number of clock main lines provided in the first peripheral region, where n is an integer being equal to or larger than 2, each of the n number of clock main lines extending in the column direction, the n number of clock main lines being configured to supply n number of types of clock signals having different phases from one another to the plurality of stages included in the shift register;
- an outer main line and an inner main line provided in the first peripheral region, each of the outer main line and the inner main line extending in the column direction, the outer main line and the inner main line being configured to supply a common signal to the plurality of stages included in the shift register;
- and
- a plurality of branch wiring lines provided in the first peripheral region, each of the plurality of branch wiring lines electrically connecting the outer main line and the inner main line,
- wherein the second peripheral region includes a terminal portion including an outer main line terminal electrically connected to the outer main line, and n number of clock main line terminals individually electrically connected to the n number of clock main lines,
- the first peripheral region includes a plurality of unit regions arrayed in the column direction, the plurality of unit regions individually corresponding to the n number of stages included in the shift register, the n number of stages being configured to be supplied with the n number of types of clock signals having different phases from one another from the n number of clock main lines,
- the plurality of branch wiring lines include at least one branch wiring line for each unit region, and
- the plurality of unit regions include a first unit region and a second unit region, the first unit region being disposed closer to the terminal portion than the second unit region, a resistance value of the at least one branch wiring line between the inner main line and the outer main line in the first unit region being smaller than a resistance value of the at least one branch wiring line between the inner main line and the outer main line in the second unit region.
Dependencies are inferred from the claim text.