Circuit board and semiconductor device including the same

A semiconductor device, comprising:

• a conductive plate having through holes extending from one side of the conductive plate to an opposite side of the conductive plate;
• a core dielectric layer, extending on the one side of the conductive plate and lining the through holes of the conductive plate;
• metallic vias formed on the core dielectric layer within the through holes of the conductive plate;
• metal pads formed on a top surface and a bottom surface of the core dielectric layer, integrally formed with the metallic vias;
• an insulating via filler disposed on the metallic vias and filling the through holes of the conductive plate;
• via caps disposed on the insulating via filler and joining with the metal pads;
• and
• dielectric layers and conductive layers alternately stacked on the opposite sides of the conductive plate,
• wherein the conductive layers are electrically connected to the metal pads, and
• the via caps, the metallic vias, and the metal pads are electrically insulated from the conductive plate.

A circuit board, comprising:

• a core layer, comprising:
• a patterned conductive plate;
• a core dielectric layer, covering all surfaces of the patterned conductive plate except for exposing a bottom surface of the patterned conductive plate;
• and
• plated through vias, extending through the patterned conductive plate and the core dielectric layer, and electrically insulated from the patterned conductive plate;
• a lower dielectric layer, extending directly on and covering the bottom surface of the patterned conductive plate, and having openings exposing portions of the plated through vias;
• a lower conductive layer, extending on the lower dielectric layer and contacting the plated through vias in the openings of the lower dielectric layer;
• an upper dielectric layer, extending on the core layer at an opposite side than the lower conductive layer, wherein the upper dielectric layer comprises openings exposing the plated through vias;
• and
• an upper conductive layer, extending on the upper dielectric layer and contacting the plated through vias in the openings of the upper dielectric layer,
• wherein the core dielectric layer and the lower dielectric layer electrically insulate the patterned conductive plate.