Prefetcher in multi-tiered memory systems
AssigneeIntel Corporation
InventorsKarthik Kumar, Francesc Cesc Guim Bernat, Thomas Willhalm, Martin P Dimitrov, Raj K. Ramanujan
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AssigneeIntel Corporation
InventorsKarthik Kumar, Francesc Cesc Guim Bernat, Thomas Willhalm, Martin P Dimitrov, Raj K. Ramanujan
Estimating the term…
Generally discussed herein are systems, devices, and methods for prefetcher in a multi-tiered memory (DSM) system. A node can include a network interface controller (NIC) comprising system address decoder (SAD) circuitry configured to determine a node identification of a node to which a memory request from a processor is homed, and prefetcher circuitry communicatively coupled to the SAD circuitry, the prefetcher circuitry to determine, based on an address in the memory request, one or more addresses from which to prefetch data, the one or more addresses corresponding to respective entries in a memory of a node on a different network than the NIC.
A network interface controller (NIC) of a first node, the NIC comprising:
A non-transitory machine-readable medium including instructions stored thereon that, when executed by a network interface controller (NIC), configure the NIC to:
A system operating in a computer network;
A network interface controller (NIC) of a first node, the comprising:
A method comprising:
Dependencies are inferred from the claim text.