Method and device for detecting the possible presence of at least one digital pattern within a signal
AssigneeSTMicroelectronics (Rousset) SAS
InventorYoann Bouvet
Life of this patent
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Abstract
In accordance with an embodiment, a device configured to detect a presence of at least one digital pattern within a signal includes J memory circuits having respectively Nj memory locations; and processing circuitry comprising an accumulator configured to successively address the memory locations of the J memory circuits in a circular manner at frequency F and during an acquisition time, and successively accumulate and store values indicative of a signal intensity in parallel in the J addressed memory locations of the J memory circuits, and a detector configured to detect the possible presence of the at least one pattern.
Claims20
A method for detecting a possible presence of at least one digital pattern within a signal, the at least one digital pattern belonging to a group of J reference patterns, J being greater than or equal to 2, comprising respectively Nj samples sequenced at a frequency F, Nj being a different integer for each reference pattern, the signal (SGN) originating from a carrier modulated by the Nj samples of the at least one digital pattern by an on-off keying modulation at frequency F for a modulation period during which the at least one digital pattern repeats at a frequency equal to F/Nj, and the samples of each reference pattern adjust an emission of the carrier, the method comprising:
- receiving the signal;
- and
- processing the received signal, processing comprising:
- (a) at the frequency F and during an acquisition time, successive circular addressing of memory locations of J memory circuits having respectively Nj memory locations, and successive accumulative storing of values indicative of a signal intensity, in parallel in the J addressed memory locations of the J memory circuits, and
- (b) detecting the possible presence of the at least one pattern, detecting comprising analyzing cumulative values contained in the memory locations of the J memory circuits.
A device for detecting a possible presence of at least one digital pattern within a signal, the at least one digital pattern belonging to a group of J reference patterns, J being greater than or equal to 2, comprising respectively Nj samples sequenced at a frequency F, Nj being a different integer for each reference pattern, the signal originating from a carrier modulated by the Nj samples of the at least one digital pattern by an on-off keying modulation at frequency F for any modulation period during which the at least one digital pattern repeats at a frequency equal to F/Nj, and the samples of each reference pattern adjust an emission of the carrier, the device comprising:
- an input interface configured to receive the signal;
- J memory circuits having respectively Nj memory locations;
- and
- processing circuitry comprising:
- an accumulator configured to
- successively address the memory locations of the J memory circuits in a circular manner at the frequency F and during an acquisition time, and
- successively accumulate and store values indicative of a signal intensity in parallel in the J addressed memory locations of the J memory circuits, and
- a detector configured to detect the possible presence of the at least one digital pattern, wherein the detector comprises an analyzer configured to analyze the accumulated values contained in the memory locations of the J memory circuits.
A circuit comprising:
- a radio receiver configured to be coupled to an antenna, the radio receiver comprising demodulator configured to convert a signal received from the antenna to a baseband signal;
- J memory circuits having respectively Nj memory locations;
- and
- processing circuitry coupled to an output of the demodulator and to the memory circuits, the processing circuitry comprising:
- an accumulator configured to
- successively address the memory locations of the J memory circuits in a circular manner at frequency F and during an acquisition time, and
- successively accumulate and store values indicative of a signal intensity of the baseband signal in parallel in the J addressed memory locations of the J memory circuits, and
- a detector configured to detect a possible presence of at least one digital pattern of the baseband signal, wherein the detector comprises an analyzer configured to analyze the accumulated values contained in the memory locations of the J memory circuits, wherein the at least one digital pattern belongs to a group of J reference patterns, J being greater than or equal to 2, comprising respectively Nj samples sequenced at a frequency F, and Nj being a different integer for each reference pattern.
Dependencies are inferred from the claim text.