Multi-stage continuous time linear equalizer with reconfigurable inductor scheme
Assignee1-Via Ltd
InventorsSuhas Rattan, Ivaylo Avramov
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Abstract
A multi-stage continuous time linear equalizer (CTLE) with a reconfigurable inductor scheme is disclosed. The multi-stage CTLE comprises a first stage transformer-based inductive peaking and a second stage resistive load. The first stage transformer-based inductive peaking is configured to control high frequency peaking and set a peak frequency value to a desired value by using a coarse equalization mechanism. The stage resistive load configured to provide tuneable equalization and low frequency fine equalization by using a fine equalization mechanism.
Claims21
A multi-stage continuous time linear equalizer (CTLE) with a reconfigurable inductor scheme, the multi-stage CTLE comprising:
- a first stage transformer-based inductive-peaking configured to control high frequency peaking and set a peaking frequency to a desired value by performing a coarse equalization mechanism, wherein the first stage transformer-based inductive-peaking comprises:
- a first active transconductance (Gm1) employed with current reuse topology to improve power consumption for a given amplification;
- a passive transformer-based inductive load based on a transformer structure comprising:
- a primary coil composed of a center-tap differential inductor (L1) configured to provide symmetric structure for signal amplification;
- a common-mode voltage (VCM) fed through a center tap;
- and
- a secondary coil electromagnetically coupled to the primary coil, wherein the secondary coil comprises a resistor (R2) placed in parallel to a secondary inductor (L2);
- and
- a load resistor (RL) electrically connected in series with the first active transconductance (Gm1) and the passive transformer-based inductive load;
- and
- a second stage resistive load configured to provide tunable low frequency fine equalization by performing a fine equalization mechanism, wherein the second stage resistive load comprises:
- a second active transconductance (Gm2) employed with current reuse topology, wherein the second active transconductance (Gm2) comprises:
- a source degeneration network of resistance and capacitance, and wherein the resistance and capacitance are implemented by using a metal-oxide semiconductor field-effect transistor (MOSFET) switch in triode and varactor diode respectively.
A multi-stage continuous time linear equalizer (CTLE) method with a reconfigurable inductor scheme, the method comprising:
- calibrating a first stage transformer-based inductive-peaking by:
- i) calibrating an inductor value in the first stage transformer-based inductive-peaking by changing a value of a resistor (R2) digitally via a digital to analog convertor (DAC) to control high frequency peaking;
- and
- ii) controlling a value of a load resistor (RL) in between a middle value of a predefined range to provide coarse equalization via controlling a low-frequency gain;
- and
- calibrating a second stage resistive load by:
- iii) calibrating fine equalization by controlling a source degeneration network of resistance and capacitance by monitoring a pulse response of an incoming signal and carrying at least one of the following two measurements:
- a) root mean square (RMS) sum of post and pre cursors and b) H2 annulment, wherein H2 is a value of the pulse response of the incoming signal after 2 unit intervals (UI);
- and
- iv) performing equalization dynamic range check to ensure the multi-stage CTLE has sufficient dynamic range to counteract effects across Process, Voltage, and Temperature (PVT) and to calibrate the second stage resistive load.
Dependencies are inferred from the claim text.