Methods and apparatus to determine and apply polarity-based error correction code

A memory controller comprising:

• a data processor having a processor output, and the data processor configured to provide first and second sets of data;
• an XOR circuit having first and second XOR inputs and an XOR output, the first XOR input coupled to the processor output, and the XOR circuit configured to:
• receive the first set of data at the first XOR input;
• receive a first polarity indicator at the second XOR input, in which the first polarity indicator corresponds to the first set of data;
• provide the first set of data in an inverted form at the XOR output based on performing a first XOR operation between the first set of data and the first polarity indicator;
• receive the second set of data at the first XOR input;
• receive a second polarity indicator at the second XOR input, in which the second polarity indicator corresponds to the second set of data;
• and
• provide the second set of data in a non-inverted form at the XOR output based on performing a second XOR operation between the second set of data and the second polarity indicator;
• and
• an encoder having first and second encoder inputs and an encoder output, the first encoder input coupled to the XOR output, and the encoder configured to:
• receive the first set of data in the inverted form at the first encoder input;
• receive the first polarity indicator at the second encoder input;
• provide first output data at the encoder output, in which the first output data include:
• the first set of data in the inverted form;
• the first polarity indicator;
• and a first set of error correction coding (ECC) data for the first set of data in the inverted form;
• receive the second set of data in the non-inverted form at the first encoder input;
• receive the second polarity indicator at the second encoder input;
• and
• provide second output data at the encoder output, in which the second output data include:
• the second set of data in the non-inverted form;
• the second polarity indicator;
• and a second set of ECC data for the second set of data in the non-inverted form.

A circuit comprising:

• a decoder configured to:
• receive first memory data from a memory array, in which the first memory data include:
• a first set of data;
• a first polarity indicator;
• and a first set of error correction coding (ECC) data for the first set of data and the first polarity indicator, and the first polarity indicator indicates whether both of the first set of data and the first set of ECC data are in an inverted form or in a non-inverted form;
• responsive to the first polarity indicator indicating that both of the first set of data and the first set of ECC data are in the inverted form, determine whether a first error is present in the first set of data using the first set of ECC data in the inverted form;
• receive second memory data from the memory array, in which the second memory data include:
• a second set of data;
• a second polarity indicator;
• and a second set of ECC data for the second set of data and the second polarity indicator, and the second polarity indicator indicates whether both of the second set of data and the second set of ECC data are in an inverted form or in a non-inverted form;
• and
• responsive to the second polarity indicator indicating that both of the second set of data and the second set of ECC data are in the non-inverted form, determine whether a second error is present in the second set of data using the second set of ECC data in the non-inverted form;
• and
• an encoder configured to:
• receive a third set of data and a third polarity indicator,
• generate a third set of ECC data for the third set of data and the third polarity indicator such that the third polarity indicator indicates whether both of the third set of data and the third set of ECC data are in an inverted form or in a non-inverted form;
• and
• provide output data to the memory array, in which the output data include:
• the third set of data;
• the third polarity indicator;
• and the third set of ECC data.