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US 11,601,137 B2Granted
ECC memory chip encoder and decoder
AssigneeIntel Corporation
InventorKjersten E. Criss
Life of this patent
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Abstract
An apparatus is described. The apparatus includes a memory chip. The memory chip has an error correction code (ECC) encoder logic circuit and an ECC decoder logic circuit. The ECC decoder logic circuit is to place an additional one or more errors that result from incorrect error correction applied to a read code word into a same block of multiple blocks of the read code word's raw data bit portion where original errors in the read code word existed before the read code word was decoded by the ECC decoder logic circuit.
Claims20
An apparatus, comprising:
- a memory chip, the memory chip comprising an error correction code (ECC) encoder logic circuit and an ECC decoder logic circuit, the ECC decoder logic circuit to place an additional one or more errors that result from incorrect error correction applied to a read code word into a same block of multiple blocks of a raw data bit portion of the read code word where original errors in the read code word existed before the read code word was decoded by the ECC decoder logic circuit.
An apparatus, comprising:
- a memory module, the memory module comprising multiple memory chips, each of the memory chips comprising the following:
- an error correction code (ECC) encoder logic circuit and an ECC decoder logic circuit, the ECC decoder logic circuit to place an additional one or more errors that result from incorrect error correction applied to a read code word into a same block of multiple blocks of a raw data bit portion of the read code word where original errors in the read code word existed before the read code word was decoded by the ECC decoder logic circuit.
A computing system, comprising:
- a plurality of processing cores;
- a main memory controller coupled to a main memory;
- and,
- an accelerator and/or graphics processing unit coupled to a local memory, wherein at least one of the main memory and local memory comprise a memory chip, the memory chip comprising an error correction code (ECC) encoder logic circuit and an ECC decoder logic circuit, the ECC decoder logic circuit to place an additional one or more errors that result from incorrect error correction applied to a read code word into a same block of multiple blocks of a raw data bit portion of the read code word where original errors in the read code word existed before the read code word was decoded by the ECC decoder logic circuit.
1 more element
Dependencies are inferred from the claim text.