Phase locked loop and operating method of phase locked loop

A phase locked loop, comprising:

• a phase detector configured to receive a reference frequency signal and a division frequency signal and to output a first signal corresponding to a phase difference of the reference frequency signal and the division frequency signal;
• a charge pump configured to receive the first signal and to amplify the first signal to output a second signal;
• a loop filter configured to receive the second signal and to filter the second signal to output a third signal;
• a voltage-to-current converter configured to receive the third signal and to convert and output the third signal into a fourth signal;
• a digital-to-analog converter configured to receive the fourth signal and a digital compensation signal and to output a fifth signal based on the fourth signal and the digital compensation signal;
• an oscillator configured to receive the fifth signal and to output an output frequency signal having a frequency corresponding to the fifth signal;
• a divider configured to receive the output frequency signal, to receive a first digital input signal from an external device, and to divide a frequency of the output frequency signal to a frequency of the division frequency signal at a division ratio defined by the first digital input signal to thus output the division frequency signal and a compensation frequency signal;
• an automatic frequency calibrator configured to receive the compensation frequency signal and the reference frequency signal and to compensate for the voltage-to-current converter based on a difference between a frequency of the compensation frequency signal and a frequency of the reference frequency signal;
• an adder configured to receive a second digital input signal from the external device, to receive a digital gain control signal from the automatic frequency calibrator, and to output, as the digital compensation signal, a sum of the first digital input signal and the digital gain control signal;
• and
• a reset circuit configured to reset the divider and the phase detector in response to which a settling operation is performed in which the division ratio is adjusted by the first digital input signal and the frequency of the output frequency signal is adjusted by the second digital input signal.

An operating method of a phase locked loop which includes a phase detector, a charge pump, a loop filter, a voltage-to-current converter, a digital-to-analog converter, an oscillator, and a divider, the operating method comprising:

• turning on all converting transistors of the digital-to-analog converter;
• dividing, at the divider, a frequency of an output frequency signal of the oscillator to generate a compensation frequency signal;
• comparing a frequency of a reference frequency signal and a frequency of the compensation frequency signal;
• and
• calibrating an amount of output current of the voltage-to-current converter, depending on a result of the comparing.