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US 11,601,120 B2Granted
Attack-resistant ring oscillators and random-number generators
AssigneeNuvoton Technology Corporation
InventorMoshe Alon
Life of this patent
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Abstract
An oscillator circuit includes a plurality of inverters connected in a cascade, at least first and second feedback taps, and alternation circuitry. The at least first and second feedback taps are configured to feed-back at least respective first and second output signals taken from at least respective first and second points in the cascade. The alternation circuitry is configured to derive an input signal from at least the first and second output signals by alternating between at least the first and second feedback taps, and to apply the input signal to an input of the cascade.
Claims13
An oscillator circuit, comprising:
- a plurality of inverters connected in a cascade;
- at least first and second feedback taps, configured to feed-back at least respective first and second output signals taken from at least respective first and second points in the cascade;
- a multiplexer, configured to multiplex at least the first and second feedback taps to the input of the cascade;
- and
- a sequence generator, configured to generate a bit sequence, and to control the multiplexer by the bit sequence,
- wherein the inverters, the first feedback tap, the second feedback tap and the multiplexer are implemented using logic gates having a uniform unit gate delay, and
- wherein (i) a first count of the logic gates, from the input of the cascade back to the input of the cascade via the first feedback tap, including a first group of the inverters, the first feedback tap and the multiplexer, and (ii) a second count of the logic gates, from the input of the cascade back to the input of the cascade via the second feedback tap, including a second group of the inverters, the second feedback tap and the multiplexer, are mutually-prime numbers.
4 more elements
A Random-Number Generator (RNG) circuit, comprising:
- a first oscillator, configured to generate a first signal in a first frequency range;
- a second oscillator, configured to generate a second signal in a second frequency range, lower than the first frequency range;
- and
- a sampling circuit, configured to output pseudo-random data by sampling the first signal using the second signal, wherein at least one of the first and second oscillators comprises:
- a plurality of inverters connected in a cascade;
- at least first and second feedback taps, configured to feed-back at least respective first and second output signals taken from at least respective first and second points in the cascade;
- a multiplexer, configured to multiplex at least the first and second feedback taps to the input of the cascade;
- and
- a sequence generator, configured to generate a bit sequence, and to control the multiplexer by the bit sequence,
- wherein the inverters, the first feedback tap, the second feedback tap and the multiplexer are implemented using logic gates having a uniform unit gate delay, and
- wherein (i) a first count of the logic gates, from the input of the cascade back to the input of the cascade via the first feedback tap, including a first group of the inverters, the first feedback tap and the multiplexer, and (ii) a second count of the logic gates, from the input of the cascade back to the input of the cascade via the second feedback tap, including a second group of the inverters, the second feedback tap and the multiplexer, are mutually-prime numbers.
8 more elements
A method, comprising:
- operating a circuit comprising (i) a plurality of inverters connected in a cascade, and (ii) at least first and second feedback taps, configured to feed-back at least respective first and second output signals taken from at least respective first and second points in the cascade;
- generating a bit sequence using a sequence generator;
- and
- controlling a multiplexer using the bit sequence to multiplex at least the first and second feedback taps to the input of the cascade,
- wherein the inverters, the first feedback tap, the second feedback tap and the multiplexer are implemented using logic gates having a uniform unit gate delay, and
- wherein (i) a first count of the logic gates, from the input of the cascade back to the input of the cascade via the first feedback tap, including a first group of the inverters, the first feedback tap and the multiplexer, and (ii) a second count of the logic gates, from the input of the cascade back to the input of the cascade via the second feedback tap, including a second group of the inverters, the second feedback tap and the multiplexer, are mutually-prime numbers.
3 more elements
Dependencies are inferred from the claim text.