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US 11,601,117 B1Granted
Sense amplifier for coupling effect reduction
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKu-Feng Lin, Jui-Che Tsai, Perng-Fei Yuh, Yih Wang
Life of this patent
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Abstract
A sense amplifier including a first input transistor having a first input gate and a first drain/source terminal, a second input transistor having a second input gate and a second drain/source terminal, a latch circuit, and a first capacitor. The latch circuit includes a first latch transistor having a third drain/source terminal connected to the first drain/source terminal and a second latch transistor having a fourth drain/source terminal connected to the second drain/source terminal. The first capacitor is connected on one side to the first input gate and on another side to the fourth drain/source terminal to reduce a coupling effect in the sense amplifier.
Claims19
A device, comprising:
- a first input transistor having a first input gate and a first drain/source terminal;
- a second input transistor having a second input gate and a second drain/source terminal;
- a latch circuit including:
- a first latch transistor having a third drain/source terminal connected to the first drain/source terminal;
- and
- a second latch transistor having a fourth drain/source terminal connected to the second drain/source terminal;
- and
- at least two capacitors connected in parallel, the at least two capacitors including:
- a first transistor capacitor having a drain and a source connected at a first terminal and a gate at a second terminal, wherein the first terminal is connected to one of the first input gate and the fourth drain/source terminal and the second terminal is connected to the other one of the first input gate and the fourth drain/source terminal;
- and
- a first metal over diffusion to metal over diffusion capacitor including:
- a first metal over diffusion layer connected to a first metal layer line;
- and
- a second metal over diffusion layer connected to a second metal layer line,
- wherein the first metal layer line is connected to one of the first input gate and the fourth drain/source terminal and the second metal layer line is connected to the other one of the first input gate and the fourth drain/source terminal.
12 more elements
A device, comprising:
- a first input transistor having a first input and a first drain/source path;
- a second input transistor having a second input and a second drain/source path;
- a latch circuit including:
- a first latch transistor having a third drain/source path connected to the first drain/source path;
- a second latch transistor having a fourth drain/source path connected to the second drain/source path;
- a third latch transistor having a fifth drain/source path connected to the third drain/source path and to one of power and a reference;
- and
- a fourth latch transistor having a sixth drain/source path connected to the fourth drain/source path and to one of the power and the reference;
- a first metal over diffusion to metal over diffusion capacitor including:
- a first metal over diffusion layer connected to a first metal layer line;
- and
- a second metal over diffusion layer connected to a second metal layer line,
- wherein the first metal layer line is connected to one of the first input and the fourth drain/source path and the second metal layer line is connected to the other one of the first input and the fourth drain/source path;
- and
- a second metal over diffusion to metal over diffusion capacitor including:
- a third metal over diffusion layer connected to a third metal layer line;
- and
- a fourth metal over diffusion layer connected to a fourth metal layer line,
- wherein the third metal layer line is connected to one of the second input and the third drain/source path and the fourth metal layer line is connected to the other one of the second input and the third drain/source path.
16 more elements
A method, comprising:
- providing a first input transistor having a first input and a first drain/source path;
- providing a second input transistor having a second input and a second drain/source path;
- connecting a third drain/source path of a first latch transistor to the first drain/source path;
- connecting a fourth drain/source path of a second latch transistor to the second drain/source path;
- connecting a first transistor capacitor having a drain and a source connected at a first terminal and a gate at a second terminal, wherein the first terminal is connected to one of the first input and the fourth drain/source path and the second terminal is connected to the other one of the first input and the fourth drain/source path;
- and
- connecting a metal over diffusion to metal over diffusion capacitor including:
- a first metal over diffusion layer connected to a first metal layer line;
- and
- a second metal over diffusion layer connected to a second metal layer line,
- wherein the first metal layer line is connected to one of the first input and the fourth drain/source path and the second metal layer line is connected to the other one of the first input and the fourth drain/source path.
8 more elements
Dependencies are inferred from the claim text.