System and method for generating sub harmonic locked frequency division and phase interpolation
AssigneeSamsung Electronics Co., Ltd.
InventorsGunjan Mandal, Vishnu Kalyanamahadevi Gopalan Jawarlal
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AssigneeSamsung Electronics Co., Ltd.
InventorsGunjan Mandal, Vishnu Kalyanamahadevi Gopalan Jawarlal
Estimating the term…
A system for generating a sub-harmonically injection locked phase interpolated output signal. The system comprises ring oscillator (RO) circuitry to generate an output oscillator signal in response to a periodic input signal. The RO circuitry includes a plurality of differential delay RO stages interconnected in cascade within a closed loop, where each RO stage is configured to establish a corresponding delayed version of the output oscillator signal successively shifted in phase by a predetermined phase difference based on a predetermined interpolation mapping scheme. The system further comprises signal injection circuitry coupled to the RO circuitry to apply a first signal having a first input phase and a second signal having a second input phase to the plurality of differential delay RO stages based on the predetermined interpolation mapping scheme to lock a frequency of the output oscillator signal at one half the frequency of the periodic input signal.
A system for generating a sub-harmonically injection locked phase interpolated output signal, the system comprising:
A method for generating a sub-harmonically injection locked phase interpolated output signal, the method comprising:
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