Transient stabilized cascode biasing

A circuit arrangement comprising:

• a stacked transistor amplifier comprising an input transistor and one or more stack transistors, the one or more stack transistors comprising an output transistor, wherein the input transistor receives an RF signal and the output transistor outputs an amplified version of the RF signal;
• a reference circuit comprising a scaled down version of the stacked transistor amplifier, the reference circuit and the stacked transistor amplifier being coupled to one another at corresponding gate nodes;
• and
• a biasing circuit configured to provide a biasing voltage to at least one gate node of a transistor of the one or more stack transistors and a corresponding gate node of a transistor of the reference circuit,
• wherein the biasing circuit comprises a feedback loop that senses a voltage at a source node of the respective transistor of the reference circuit and controls the biasing voltage to the at least one gate node so that a sensed voltage at said source node is equal to a reference voltage,
• wherein control of the biasing voltage is provided by charging and discharging of a capacitor that is coupled between said gate node and a reference ground by a current output by the feedback loop, and
• wherein coupling of the stacked transistor amplifier to the reference circuit is provided via respective series connected resistors that are configured to substantially isolate the reference circuit from the RF signal.