Deeply integrated voltage regulator architectures
AssigneeNavitas Semiconductor Limited
InventorDavid Lidsky
Life of this patent
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Abstract
A system is disclosed. The system includes a substrate, and a first chip on the substrate, where a load circuit is integrated on the first chip. The system also includes a second chip on the substrate, where a power delivery circuit is configured to deliver current to the load circuit according to a regulated voltage at a node. The power delivery circuit includes a first circuit configured to generate an error signal based at least in part on the regulated voltage, and a voltage generator including power switches configured to modify the regulated voltage according to the error signal, where the first circuit of the power delivery circuit is integrated on the first chip, and where at least a portion of the power switches of the power delivery circuit are integrated on the second chip.
Claims20
A system comprising:
- a substrate;
- a first semiconductor die disposed on the substrate and including a load circuit and an error signal generation circuit;
- and
- a second semiconductor die disposed on the substrate and including a power converter circuit arranged to deliver power to the load circuit, the power converter circuit including a plurality of power switches coupled to a control circuit;
- wherein the control circuit receives an error signal from the error signal generation circuit and in response controls a power delivered to the load circuit via the plurality of power switches.
A method of forming a system, the method comprising:
- attaching a first semiconductor die to a substrate, the first semiconductor die including a load circuit and an error signal generation circuit;
- and
- attaching a second semiconductor die to the substrate, the second semiconductor die including a power converter circuit arranged to deliver power to the load circuit, the power converter circuit including a plurality of power switches coupled to a control circuit;
- wherein the control circuit receives an error signal from the error signal generation circuit and in response controls a power delivered to the load circuit via the plurality of power switches.
Dependencies are inferred from the claim text.