Dummy FIN profile control to enlarge gate process window

A device comprising:

• a semiconductor substrate;
• isolation regions over a bulk portion of the semiconductor substrate;
• a semiconductor fin protruding higher than top surfaces of the isolation regions, wherein the semiconductor fin has a first lengthwise direction;
• and
• a dielectric dummy fin protruding higher than the top surfaces of the isolation regions, wherein the dielectric dummy fin has a second lengthwise direction parallel to the first lengthwise direction, wherein the dielectric dummy fin has a top width and a bottom width greater than the top width, with the top width and the bottom width being measured in a widthwise direction perpendicular to the first lengthwise direction, and wherein the dielectric dummy fin has a first top surface lower than a second top surface of the semiconductor fin.

A device comprising:

• a dielectric dummy fin;
• a first protruding semiconductor fin and a second protruding semiconductor fin on opposing sides of the dielectric dummy fin, wherein a first top surface of the dielectric dummy fin is lower than second top surfaces of the first protruding semiconductor fin and the second protruding semiconductor fin;
• a first gate stack on the first protruding semiconductor fin;
• a second gate stack on the second protruding semiconductor fin;
• and
• a gate isolation region between, and contacting, the first gate stack and the second gate stack, wherein the gate isolation region is over and contacting the dielectric dummy fin.