Semiconductor device and method

A method comprising:

• forming a dummy gate layer over a substrate;
• forming first openings in the dummy gate layer, comprising:
• performing a first plasma etching process comprising a first pulsed bias voltage having a first duty cycle, the first duty cycle associated with a first desired metal gate width at a first height above the substrate, wherein the first plasma etching process forms a first recess, wherein a bottom surface of the first recess comprises remaining portions of the dummy gate layer;
• after performing the first plasma etching process, performing a second plasma etching process comprising a second pulsed bias voltage having a second duty cycle, the second duty cycle associated with a second desired metal gate width at a second height above the substrate, wherein at least one of the first pulsed bias voltage and the first duty cycle is different than the second pulsed bias voltage and the second duty cycle, respectively, wherein the second plasma etching process recesses the remaining portions of the dummy gate layer to form a second recess, wherein the second recess comprises a first tapered sidewall of the dummy gate layer;
• and
• after performing the second plasma etching process, performing a third plasma etching process comprising a third pulsed bias voltage having a third duty cycle, the third duty cycle associated with a third desired metal gate width at a third height above the substrate, wherein at least one of the second pulsed bias voltage and the second duty cycle is different than the third pulsed bias voltage and the third duty cycle, respectively, wherein the third plasma etching process widens the second recess;
• forming a dielectric material in the first openings;
• removing remaining portions of the dummy gate layer to form second openings;
• and
• forming a metal gate in the second openings, the metal gate having the first desired metal gate width at the first height above the substrate, the second desired metal gate width at the second height above the substrate, and the third desired metal gate width at the third height above the substrate.

A method comprising:

• forming a semiconductor fin protruding a first height above a substrate;
• forming an isolation region adjacent the semiconductor fin, the semiconductor fin protruding above the isolation region;
• forming a dummy gate material over and adjacent the semiconductor fin, and over the isolation region;
• performing a first plasma etching process using a first set of plasma etching parameters on the dummy gate material to form a first recess, wherein a sidewall of the first recess forms a first portion of a dummy gate stack having a first width at the first height, wherein the first portion of the dummy gate stack has a tapering profile, wherein the first plasma etching process only partially etches through the dummy gate material over the isolation region;
• after forming the first portion of the dummy gate stack, performing a second plasma etching process using a second set of plasma etching parameters to remove the dummy gate material on a bottom of the first recess to form a second recess, a sidewall of the second recess forms a second portion of the dummy gate stack having a second width that is different from the first width, wherein the first set of plasma etching parameters is different than the second set of plasma etching parameters, wherein the first portion of the dummy gate stack has a first sidewall slope and the second portion of the dummy gate stack has a second sidewall slope that is different from the first sidewall slope, wherein a width of the dummy gate stack adjacent a top of the semiconductor fin is less than a width of the dummy gate stack adjacent a top of the isolation region;
• and
• after forming the second portion, performing a third plasma etching process on the second portion to alter the second sidewall slope and widen the second recess.