Sub-fin leakage reduction for template strained materials
AssigneeIntel Corporation
InventorsRishabh Mehandru, Stephen Cea, Anupama Bowonder, Juhyung Nam, Willy Rachmady
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Abstract
Embodiments disclosed herein include transistor devices and methods of forming such transistor devices. In an embodiment a transistor comprises a substrate, and a fin that extends up from the substrate. In an embodiment, the fin comprises a source region, a drain region, and a channel region between the source region and the drain region. In an embodiment, the transistor further comprises and a cavity in the fin, where the cavity is below the channel region. In an embodiment, the transistor further comprises a gate stack over the fin.
Claims16
A transistor, comprising:
- a substrate;
- a fin extending up from the substrate, wherein the fin comprises:
- a source region;
- a drain region;
- and
- a channel region between the source region and the drain region;
- a cavity in the fin, wherein the cavity is below the channel region;
- and
- a gate stack over the fin.
An electronic system, comprising:
- a board;
- an electronic package electrically coupled to the board;
- and
- a semiconductor die electrically coupled to the electronic package, wherein the semiconductor die comprises:
- a non-planar transistor, wherein the non-planar transistor comprises:
- a channel region between a source region and a drain region;
- a cavity in below the channel region;
- and
- a gate stack over at least a first surface and a second surface of the channel region.
Dependencies are inferred from the claim text.