Display device and method of fabricating the same

A display device comprising:

• a substrate;
• a first conductive layer on the substrate and including a signal line;
• a buffer layer on the first conductive layer;
• a semiconductor pattern on the buffer layer;
• a gate insulating layer on the semiconductor pattern;
• a gate electrode on the gate insulating layer;
• a passivation layer on the gate electrode;
• a planarization layer on the passivation layer;
• and
• a second conductive layer on the planarization layer and including a conductive pattern electrically coupling the semiconductor pattern to the signal line,
• wherein the conductive pattern is coupled to the signal line through a first contact hole passing through the planarization layer and the buffer layer, and coupled to the semiconductor pattern through a second contact hole passing through the planarization layer,
• wherein the second conductive layer further includes a second conductive pattern spaced apart from the first conductive pattern, and the second conductive pattern electrically couples the semiconductor pattern to a lower light blocking pattern,
• wherein the first contact hole and the second contact hole pass through the passivation layer, and the passivation layer covers at least a portion of a top surface of the substrate while covering a top surface of the gate electrode.

A method of fabricating a display device, the method comprising:

• depositing a first conductive layer material, a buffer layer material and a semiconductor layer material entirely on a substrate;
• etching the first conductive layer material, the buffer layer material and the semiconductor layer material using a mask having a light blocking part and two or more light transmitting parts having different light transmittances to pattern a first conductive layer including a lower light blocking pattern, a buffer layer and a semiconductor layer;
• forming a gate insulating layer on the semiconductor layer;
• forming a second conductive layer including a gate electrode on the gate insulating layer;
• forming a planarization layer on the second conductive layer;
• and
• forming a third conductive layer on the planarization layer, the third conductive layer including a first conductive pattern electrically coupling the lower light blocking pattern to the semiconductor layer,
• wherein the first conductive pattern is coupled to the lower light blocking pattern through a first contact hole passing through the planarization layer and the buffer layer, and coupled to the semiconductor layer through a second contact hole passing through the planarization layer,
• wherein the first conductive layer further includes a signal line, and the third conductive layer is spaced apart from the first conductive layer, and further includes a second conductive pattern electrically coupling the semiconductor layer to the signal line, and
• wherein the second conductive pattern is coupled to the signal line through a third contact hole passing through the planarization layer and the buffer layer, and coupled to the semiconductor layer through a fourth contact hole passing through the planarization layer.