Method to produce 3D semiconductor devices and structures with memory

A method for producing a 3D semiconductor device, the method comprising:

• providing a first level, said first level comprising a first single crystal layer;
• forming first alignment marks and control circuits in and/or on said first level,
• wherein said control circuits comprise first single crystal transistors, and
• wherein said control circuits comprise at least two interconnection metal layers;
• forming at least one second level disposed above said control circuits;
• performing a first etch step into said second level;
• forming at least one third level disposed on top of said second level;
• performing additional processing steps to form a plurality of first memory cells within said second level and a plurality of second memory cells within said third level,
• wherein each of said plurality of first memory cells comprise at least one second transistor,
• wherein each of said plurality of second memory cells comprise at least one third transistor,
• wherein said additional processing steps comprise depositing a gate electrode simultaneously for said second transistors and said third transistors;
• and
• performing bonding of said first level to said second level,
• wherein said bonding comprises oxide to oxide bonding.

A method for producing a 3D semiconductor device, the method comprising:

• providing a first level, said first level comprising a first single crystal layer;
• forming first alignment marks and control circuits in and/or on said first level,
• wherein said control circuits comprise first single crystal transistors, and
• wherein said control circuits comprise at least two interconnection metal layers;
• forming at least one second level disposed above said control circuits;
• performing a first etch step into said second level;
• forming at least one third level disposed on top of said second level;
• performing additional processing steps to form a plurality of first memory cells within said second level and a plurality of second memory cells within said third level,
• wherein each of said plurality of first memory cells comprise at least one second transistor,
• wherein each of said plurality of second memory cells comprise at least one third transistor,
• wherein said performing additional processing steps comprises using Atomic Layer Deposition (ALD);
• and
• performing bonding of said first level to said second level,
• wherein said bonding comprises oxide to oxide bonding.