Memory cell and memory array select transistor
AssigneeZeno Semiconductor, Inc.
InventorsJin-Woo Han, Yuniarto Widjaja
Life of this patent
Estimating the term…
Abstract
A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) with increased on-state current obtained through a parasitic bipolar junction transistor (BJT) of the MOSFET. Methods of operating the MOSFET as a memory cell or a memory array select transistor are provided.
Claims21
A semiconductor device configured to function as a memory select transistor with increased on-state drain current;
- said semiconductor device comprising:
- a substrate having a first conductivity type selected from p-type conductivity type and n-type conductivity type;
- a buried layer having a second conductivity type selected from said p-type conductivity type and said n-type conductivity type and being different from said first conductivity type;
- a body having said first conductivity type;
- a source region and a drain region each having said second conductivity type and being separated by said body;
- a gate positioned in between said source region and said drain region;
- a charge trap layer containing a substantial number of charge trap centers that may absorb excess majority carrier, said charge trap layer contacting at least one of said source region and said drain region;
- and
- an insulating layer comprising an STI contacting said charge trap layer;
- wherein said semiconductor device is configured to function as a select transistor for at least one memory element connected to said drain region or said source region, wherein a state of said at least one memory element is determined by a resistivity of said at least one memory element.
A semiconductor memory device comprising a first semiconductor device as a first memory select transistor, a second semiconductor device as a second memory select transistor and a memory element, wherein said first memory select transistor comprises a first floating body region, said second memory select transistor comprises a second floating body region, and said semiconductor memory device functions as a dual-port memory device, wherein said semiconductor memory device is configured so that read and write operations to said memory element can be simultaneously performed via first and second ports of said dual-port memory device.
Dependencies are inferred from the claim text.