Imaging element
AssigneeSony Semiconductor Solutions Corporation
InventorsKeiichi Nakazawa, Yoshiaki Kitano, Hirofumi Yamashita, Minoru Ishida
Life of this patent
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Abstract
An imaging element according to an embodiment of the present disclosure includes: a first substrate, a second substrate, and a third substrate that are stacked in this order. The first substrate including a sensor pixel that performs photoelectric conversion and the second substrate including a readout circuit are electrically coupled to each other by a first through wiring line provided in an interlayer insulating film. The second substrate and the third substrate including a logic circuit are electrically coupled to each other by a junction between pad electrodes or a second through wiring line penetrating through a semiconductor substrate.
Claims20
An imaging element, comprising:
- a first substrate including a sensor pixel in a first semiconductor substrate, the sensor pixel performing photoelectric conversion;
- a second substrate including a readout circuit in a second semiconductor substrate, the readout circuit outputting a pixel signal on a basis of an electric charge outputted from the sensor pixel;
- and
- a third substrate including a logic circuit in a third semiconductor substrate, the logic circuit processing the pixel signal,
- wherein the first substrate, the second substrate, and the third substrate are stacked in this order,
- wherein a stacked body of the first substrate and the second substrate includes an interlayer insulating film and a first through wiring line provided in the interlayer insulating film,
- wherein the first substrate and the second substrate are electrically coupled to each other by the first through wiring line,
- wherein the third substrate includes a second through wiring line penetrating through the third semiconductor substrate,
- wherein the second substrate and the third substrate are electrically coupled to each other by the second through wiring line, and
- wherein a cross-sectional area throughout the first through wiring line is smaller than a cross-sectional area throughout the second through wiring line.
An imaging element, comprising:
- a first substrate including a sensor pixel of a plurality of sensor pixels in a first semiconductor substrate;
- a second substrate including a readout circuit in a second semiconductor substrate outputting a pixel signal;
- and
- a third substrate including a logic circuit in a third semiconductor substrate processing the pixel signal,
- wherein a stacked body of the first substrate and the second substrate includes an interlayer insulating film and a first through wiring line of a plurality of first through wiring lines electrically coupling the first substrate and the second substrate provided in the interlayer insulating film,
- wherein the third substrate includes a second through wiring line of a plurality of second through wiring lines electrically coupling the second substrate and the second substrate penetrating through the third semiconductor substrate, and
- wherein a cross-sectional area throughout the first through wiring line is smaller than a cross-sectional area throughout the second through wiring line.
Dependencies are inferred from the claim text.