Floating gate memory cell and memory array structure
AssigneeGlobalFoundries U.S. Inc.
InventorThomas Melde
Life of this patent
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Abstract
Embodiments of the disclosure provide a floating gate memory cell, including: a silicon-on-insulator (SOI) substrate, the SOI substrate including a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate, and a semiconductor layer formed on the buried oxide layer; a memory device, including: a control gate formed in the semiconductor layer of the SOI substrate; an insulating layer formed on the control gate; and a floating gate formed on the insulating layer; and a transistor device electrically connected to the memory device. The transistor device includes an active region formed in the semiconductor layer of the SOI substrate.
Claims14
A method of manufacturing a floating gate memory cell, comprising:
- forming a memory device on a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate, and a semiconductor layer formed on the buried oxide layer, wherein forming the memory device comprises:
- forming a control gate in the semiconductor layer of the SOI substrate;
- forming an insulating layer on the control gate;
- and
- forming a floating gate on the insulating layer;
- and
- forming a transistor device on the SOI substrate, wherein an active region of the transistor device is formed in the bulk semiconductor layer of the SOI substrate.
A floating gate memory cell, comprising:
- a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate, and a semiconductor layer formed on the buried oxide layer;
- a memory device, comprising:
- a control gate formed in the semiconductor layer of the SOI substrate;
- an insulating layer formed on the control gate;
- and
- a floating gate formed on the insulating layer;
- and
- a transistor device electrically connected to the memory device, wherein an active region of the transistor device is formed in the bulk semiconductor layer of the SOT substrate.
A memory array, comprising:
- a plurality of floating gate memory cells, each floating gate memory cell comprising:
- a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate, and a semiconductor layer formed on the buried oxide layer;
- a memory device, comprising:
- a control gate formed in the semiconductor layer of the SOI substrate;
- an insulating layer formed on the control gate;
- and
- a floating gate formed on the insulating layer;
- and
- an active area electrically connected to the memory device, wherein the active area is formed in the bulk semiconductor layer of the SOI substrate,
- wherein each floating gate memory cell further comprises a gate electrically connecting the control gate of the memory device to the active area.
Dependencies are inferred from the claim text.