Semiconductor structure with dielectric fin in memory cell and method for forming the same

A semiconductor structure, comprising:

• a pull-up transistor over a substrate, the pull-up transistor comprising a first channel region of a first semiconductor fin and a first source/drain structure over the first semiconductor fin;
• a pull-down transistor adjacent to the pull-up transistor, the pull-down transistor comprising a first channel region of a second semiconductor fin and a second source/drain structure over the second semiconductor fin;
• an insulating liner between the first semiconductor fin and the second semiconductor fin;
• and
• a dielectric fin interposing the first source/drain structure and the second source/drain structure and including a bottom potion embedded in the insulating liner.

A method for forming a semiconductor structure, comprising:

• forming a first semiconductor fin and a second semiconductor fin over a substrate;
• forming an insulating material over the first semiconductor fin and the second semiconductor fin;
• forming a dielectric layer over the insulating material and filling a gap between the first semiconductor fin and the second semiconductor fin;
• polishing the dielectric layer and the insulating material until the first semiconductor fin and the second semiconductor fin are exposed, wherein a remaining portion of the dielectric layer forms a dielectric fin;
• recessing the insulating material to expose sidewalls of the dielectric fin;
• forming a dummy gate structure across the first semiconductor fin, the dielectric fin and the second semiconductor fin;
• and
• forming a first source/drain structure over the first semiconductor fin and a second source/drain structure over the second semiconductor fin.