Well pick-up region design for improving memory macro performance

A memory macro, comprising:

• a memory bit cell region;
• a first well pick-up (WPU) region on a first side of the memory bit cell region;
• a second WPU region on the first side of the memory bit cell region, wherein the memory bit cell region, the first WPU region, and second WPU region are arranged along a first direction in sequence;
• and
• n-type wells and p-type wells arranged alternately in the memory bit cell region along a second direction perpendicular to the first direction, wherein the n-type wells extend along the first direction into the first WPU region, wherein at least one of the p-type wells extends along the first direction across the first WPU region and into the second WPU region,
• wherein at least one of the n-type wells has a first width in the first WPU region measured along the second direction and a second width in the memory bit cell region measured along the second direction, and wherein the first width is larger than the second width.

A layout of a static random access memory (SRAM) array, comprising:

• a memory bit cell area;
• a well pick-up (WPU) area adjacent to the memory bit cell area;
• a n-type well and a p-type well each oriented lengthwise along a first direction in the memory bit cell area and the WPU area, the n-type and p-type wells having a well boundary therebetween;
• a first fin oriented lengthwise along the first direction in the memory bit cell area and the WPU area, the first fin having a length measured along the first direction and a width measured along a second direction perpendicular to the first direction, the length being larger than the width, the first fin including a first segment in the WPU area and over the n-type well and a second segment in the memory bit cell area and over the p-type well, the second segment being disconnected from the first segment;
• and
• gate structures over the first fin in the memory bit cell area and oriented lengthwise along the second direction.