Integrated circuit structure and manufacturing method thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHarry-Hak-Lay Chuang, Li-Feng Teng, Wei-Cheng Wu, Fang-Lan Chu, Ya-Chen Kao
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Abstract
A includes depositing a gate electrode layer over a semiconductor substrate; patterning the gate electrode layer into a first gate electrode and a gate electrode extending portion; forming a first gate spacer alongside the first gate electrode; patterning the gate electrode extending portion into a second gate electrode after forming the first gate spacer; and forming a second gate spacer alongside the second gate electrode and a third gate spacer around the first spacer.
Claims20
A method comprising:
- forming a semiconductor fin over a semiconductor substrate;
- depositing a gate electrode layer over the semiconductor substrate;
- patterning the gate electrode layer into a first gate electrode and a gate electrode extending portion, wherein patterning the gate electrode layer is performed such that the gate electrode extending portion is over the semiconductor fin;
- forming a first gate spacer alongside the first gate electrode;
- patterning the gate electrode extending portion into a second gate electrode after forming the first gate spacer;
- and
- forming a second gate spacer alongside the second gate electrode and a third gate spacer around the first gate spacer.
A method comprising:
- forming a semiconductor fin over a first region of a semiconductor substrate;
- forming an isolation structure surrounding the semiconductor fin;
- depositing a first dielectric layer over a second region of the semiconductor substrate after forming the isolation structure;
- recessing a top surface of the isolation structure to a level lower than a top of the semiconductor fin;
- forming a first gate structure over the semiconductor fin;
- and
- forming a second gate structure over the second region of the semiconductor substrate, wherein the second gate structure is larger than the first gate structure from a top view.
An integrated circuit (IC) structure, comprising:
- a semiconductor substrate;
- a first gate electrode over a first region of the semiconductor substrate;
- a first gate spacer alongside the first gate electrode;
- a first source/drain feature adjacent to the first gate spacer;
- a second gate electrode over a second region of the semiconductor substrate, the second gate electrode being larger than the first gate electrode from a top view;
- a second gate spacer alongside the second gate electrode, wherein a width of the second gate spacer is greater than a width of the first gate spacer;
- and
- a second source/drain feature adjacent to the second gate spacer, wherein a first distance between the first gate electrode and the first source/drain feature is less than a second distance between the second gate electrode and the second source/drain feature.
Dependencies are inferred from the claim text.