Semiconductor device including FINFETs having different channel heights

A semiconductor device, comprising:

• a first fin field effect transistor (FinFET);
• and
• a second FinFET, wherein:
• a fin channel height of the first FinFET is greater than a fin channel height of the second FinFET,
• the first FinFET includes:
• a first fin structure continuously protruding from a semiconductor substrate, a first channel region of the first fin structure protruding from a first isolation insulating layer provided over the substrate, and a bottom part of the first fin structure below the first channel region being embedded in the first isolation insulating layer;
• and
• a first gate dielectric layer disposed over the first channel region of the fin structure;
• a first gate electrode layer disposed over the first gate dielectric layer,
• the second FinFET includes:
• a second fin structure continuously protruding from the semiconductor substrate, a second channel region of the second fin structure protruding from a second isolation insulating layer disposed over the first isolation insulating layer, and a bottom part of the second fin structure below the second channel region being embedded in the first and second isolation insulating layers;
• a second gate dielectric layer disposed over the second channel region of the fin structure;
• and
• a second gate electrode layer disposed over the second gate dielectric layer,
• the fin channel height of the first FinFET is measured from an interface between the first gate dielectric layer and the first isolation insulating layer, and
• the fin channel height of the second FinFET is measured from an interface between the second gate dielectric layer and the second isolation insulating layer.

A semiconductor static random access memory (SRAM), comprising a first pass-gate transistor, a second pass-gate transistor, a first pull-up transistor, a second pull-up transistor, a first pull-down transistor and a second pull-down transistor, each of which is formed by a fin field effect transistor (FinFET), wherein:

• a first fin channel height of the FinFETs of the first and second pull-down transistors is greater than at least one of a second fin channel height of the FinFETs of the first and second pass-gate transistors and a third fin channel height of the FinFETs of the first and second pull-up transistors,
• each of the FinFETs of the first and second pull-down transistors includes:
• a first fin structure continuously protruding from a semiconductor substrate, a first channel region of the first fin structure protruding from a first isolation insulating layer provided over the substrate, and a bottom part of the first fin structure below the first channel region being embedded in the first isolation insulating layer;
• and
• at least one of the FinFETs of the first and second pass-gate transistors and the FinFETs of the first and second pull-up transistors includes:
• a second fin structure continuously protruding from the semiconductor substrate, a second channel region of the second fin structure protruding from a second isolation insulating layer, and a bottom part of the second fin structure below the second channel region being embedded in the second isolation insulating layer;
• the first fin channel height is measured from an upper surface of the first isolation insulating layer, and
• at least one of the second or third fin channel heights is measured from an upper surface of the second isolation insulating layer.