Three-dimensional semiconductor memory device and electronic system including the same

A three-dimensional semiconductor memory device, comprising:

• a first structure;
• and
• a second structure in contact with the first structure,
• wherein each of the first and second structures comprises:
• a substrate;
• a peripheral circuit region comprising a plurality of peripheral transistors on the substrate, a plurality of peripheral circuit lines on the peripheral transistors, and a plurality of first bonding pads connected to the peripheral transistors through the peripheral circuit lines;
• and
• a cell array region comprising a plurality of second bonding pads which are integrally bonded with respective ones of the first bonding pads of the peripheral circuit region, a plurality of connection circuit lines on the second bonding pads, a plurality of bit lines connected to the second bonding pads through the connection circuit lines, a stack structure on the bit lines, a plurality of vertical structures that penetrate the stack structure, a common source region in contact with the vertical structures, and a source conductive pattern between the stack structure and the common source region,
• wherein the stack structure is between the peripheral circuit region and the common source region,
• wherein the common source regions of the first and second structures are connected to each other,
• wherein each of the vertical structures is in a respective vertical channel that penetrates the stack structure,
• wherein each of the vertical structures comprises a data storage pattern that conformally covers an inner wall of the respective vertical channel and a vertical semiconductor pattern surrounded by the data storage pattern,
• wherein the data storage pattern comprises a blocking dielectric layer, a charge storage layer, and a tunneling dielectric layer that are sequentially stacked, and
• wherein the source conductive pattern is in contact with the vertical semiconductor pattern.

An electronic system, comprising:

• a three-dimensional semiconductor memory device that comprises a first structure, a second structure, and an input/output pad,
• wherein each of the first and second structures comprises:
• a substrate;
• a peripheral circuit region on the substrate;
• and
• a cell array region comprising a stack structure on the peripheral circuit region, a plurality of vertical structures that penetrate the stack structure, and a common source region in contact with the vertical structures,
• wherein the input/output pad is connected to the peripheral circuit region of the second structure;
• and
• a controller that is electrically connected to the three-dimensional semiconductor memory device through the input/output pad and is configured to control the three-dimensional semiconductor memory device,
• wherein the stack structure is between the peripheral circuit region and the common source region,
• wherein the common source regions of the first and second structures are connected with each other,
• wherein the cell array region further comprises a source conductive pattern between the stack structure and the common source region, and
• wherein the source conductive pattern is in contact with a sidewall of the vertical structure.