Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorsJichul Kim, Chajea Jo, Sang-Uk Han, Kyoung Soon Cho, Jae Choon Kim, Woohyun Park
Life of this patent
Estimating the term…
Abstract
A semiconductor package includes a first semiconductor chip on a substrate, a second semiconductor chip on the substrate and spaced apart from the first semiconductor device, a mold layer on the substrate and covering sides of the first and second semiconductor chips, and an image sensor unit on the first and second semiconductor chips and the mold layer. The image sensor unit is electrically connected to the first semiconductor chip.
Claims20
A method of manufacturing a semiconductor package, the method comprising:
- aligning a first chip on a second chip so that a first active surface of the first chip faces a second active surface of the second chip;
- bonding the first chip and the second chip by a direct bonding process, the first active surface of the first chip and the second active surface of the second chip are in contact with each other;
- forming a redistribution layer on a non-active surface of the second chip to electrically connect to the redistribution layer and the second chip;
- mounting a third chip and a fourth chip on the redistribution layer, the third chip and the fourth chip spaced laterally apart from each other;
- and forming a molding layer below the redistribution layer to cover sides of the third chip and the fourth chip, wherein the first chip comprises a first bonding pad on the first active surface, and the second chip comprises a second bonding pad on the second active surface, and wherein the first bonding pad and the second bonding pad are in direct contact to electrically connect between the first chip and the second chip.
A method of manufacturing a semiconductor package, the method comprising:
- forming a first semiconductor chip in a first semiconductor substrate;
- forming a second semiconductor chip in a second semiconductor substrate;
- bonding the first semiconductor substrate on the second semiconductor substrate to electrically connect the first semiconductor chip and the second semiconductor chip;
- exposing a via of the second semiconductor chip on a bottom surface of the second semiconductor substrate;
- forming a redistribution layer below the second semiconductor substrates to electrically connect to the via;
- mounting a third semiconductor chip and a fourth semiconductor chip spaced laterally apart from each other on the redistribution layer;
- forming a molding layer below the redistribution layer to surround the third semiconductor chip and the fourth semiconductor chip;
- and
- sawing the first semiconductor substrate, the second semiconductor substrate and the molding layer,
- wherein the first semiconductor chip comprises a first bonding pad on a first active surface of the first semiconductor chip, and the second semiconductor chip comprises a second bonding pad on a second active surface of the second semiconductor chip, and
- wherein the first bonding pad and the second bonding pad are in direct contact to electrically connect between the first semiconductor chip and the second semiconductor chip.
Dependencies are inferred from the claim text.