Semiconductor package including stacked semiconductor chips

A semiconductor package comprising:

• a first semiconductor chip stack including a plurality of first semiconductor chips which are stacked in a vertical direction;
• a bridge die stack disposed to be spaced apart from the first semiconductor chip stack in a horizontal direction and including a plurality of bridge dies which are stacked in the vertical direction, wherein the bridge dies include through electrodes, respectively, and the through electrodes aligned in the vertical direction are connected to each other through a connection electrode between the bridge dies;
• a redistribution layer disposed over the first semiconductor chip stack and the bridge die stack;
• a second semiconductor chip disposed over the redistribution layer and configured to receive a voltage through the through electrodes aligned in the vertical direction, the connection electrode, and the redistribution layer;
• and
• a voltage regulator configured to adjust the voltage, wherein the voltage regulator comprises:
• a switch included in at least one of the bridge dies;
• a diode included in at least one of the bridge dies;
• a capacitor included in at least one of the bridge dies;
• an inductor included in the redistribution layer;
• and
• a controller included in the second semiconductor chip.