Method of forming RDLS and structure formed thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHung-Jui Kuo, Yun Chen Hsieh, Hui-Jung Tsai, Chen-Hua Yu
Life of this patent
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Abstract
A method includes encapsulating a device die in an encapsulating material, planarizing the device die and the encapsulating material, and forming a first plurality of conductive features electrically coupling to the device die. The step of forming the first plurality of conductive features includes a deposition-and-etching process, which includes depositing a blanket copper-containing layer, forming a patterned photo resist over the blanket copper-containing layer, and etching the blanket copper-containing layer to transfer patterns of the patterned photo resist into the blanket copper-containing layer.
Claims20
A structure comprising:
- a device die;
- a first plurality of conductive features over and electrically coupling to the device die, wherein the first plurality of conductive features have first sidewalls with first tilt angles smaller than about 85 degrees, and wherein entireties of the first plurality of conductive features are formed of a homogeneous material;
- and
- a second plurality of conductive features over and electrically coupling to the first plurality of conductive features, wherein the second plurality of conductive features have second sidewalls with second tilt angles greater than about 85 degrees, with all of the second tilt angles being greater than all of the first tilt angles, and wherein each of the second plurality of conductive features comprises a titanium layer and a copper layer over the titanium layer.
A structure comprising:
- a device die;
- a plurality of redistribution layers over the device die, wherein each of the plurality of redistribution layers comprises a plurality of redistribution lines;
- a first via layer comprising a first plurality of vias having first sidewalls with first tilt angles, wherein the first plurality of vias have first pitches, and the first plurality of vias are free from seed layers, wherein the first via layer is between two layers in the plurality of redistribution layers;
- and
- a second via layer comprising a second plurality of vias having second sidewalls with second tilt angles greater than the first tile angles, wherein the second plurality of vias have second pitches greater than the first pitches, and each of the second plurality of vias comprises a seed layer and a metal layer over the seed layer, and wherein the second via layer is between additional two layers in the plurality of redistribution layers.
A structure comprising:
- a device die;
- an encapsulant encapsulating the device die therein;
- a plurality of dielectric layers over the encapsulant and the device die;
- a plurality of redistribution layers over the device die, wherein each of the plurality of redistribution layers comprises a plurality of redistribution lines;
- a first plurality of conductive features in a first layer in the plurality of redistribution layers, wherein first edges of the first plurality of conductive features have first tilt angles;
- and
- a second plurality of conductive features in a second layer in the plurality of redistribution layers, with the second layer being immediately over and contacting the first layer, wherein second edges of the second plurality of conductive features have second tilt angles, and each of the second tilt angles is greater than all of the first tilt angles, wherein all of the plurality of redistribution layers over the second layer have conductive features with sidewalls having tilt angles greater than all of the first tilt angles, and wherein all of the plurality of redistribution layers underlying the first layer have conductive features with tilt angles smaller than all of the second tilt angles.
Dependencies are inferred from the claim text.