Integrated circuit device and method of manufacturing the same

An integrated circuit device, comprising:

• a fin-type active region extending on a substrate in a first horizontal direction;
• a gate line extending on the fin-type active region in a second horizontal direction crossing the first horizontal direction;
• a pair of source/drain regions on the fin-type active region and adjacent to the gate line;
• a first conductive plug connected to a first source/drain region from among the pair of source/drain regions, the first conductive plug including a first metal film comprising a first metal and a first metal liner surrounding the first metal film;
• and
• a complex capping layer covering a top surface of the first conductive plug,
• wherein the complex capping layer comprises:
• a conductive alloy capping layer comprising a first semiconductor element and a second metal different from the first metal, and covering a top surface of the first metal film;
• an insulating capping layer covering the conductive alloy capping layer and the gate line;
• and
• a nitrated alloy layer disposed between the conductive alloy capping layer and the insulating capping layer, the nitrated alloy layer comprising the second metal, the first semiconductor element, and nitrogen atoms.

An integrated circuit device, comprising:

• a plurality of fin-type active regions extending on a substrate in a first horizontal direction to be parallel to each other;
• a gate line extending on the plurality of fin-type active regions in a second horizontal direction crossing the first horizontal direction;
• a plurality of source/drain regions on the plurality of fin-type active regions;
• a first conductive plug connected to a plurality of first source/drain regions from among the plurality of source/drain regions, the first conductive plug overlapping the plurality of fin-type active regions;
• a second conductive plug connected to a plurality of second source/drain regions from among the plurality of source/drain regions, the second conductive plug overlapping the plurality of fin-type active regions, and being spaced apart from the first conductive plug with the gate line interposed between the first conductive plug and the second conductive plug;
• and
• a complex capping layer covering top surfaces of the first conductive plug and the second conductive plug,
• wherein each of the first conductive plug and the second conductive plug includes a first metal film comprising a first metal and a first metal liner surrounding the first metal film, and
• wherein the complex capping layer comprises:
• a plurality of first conductive alloy capping layers each comprising a first semiconductor element and a second metal different from the first metal, wherein each of the top surfaces of the first conductive plug and the second conductive plug is covered with one of the plurality of first conductive alloy capping layers;
• a plurality of second conductive alloy capping layers each comprising the first metal and a second semiconductor element, wherein each of the second conductive alloy capping layer is disposed between the first metal film and one of the plurality of first conductive alloy capping layers;
• and
• an insulating capping layer covering the plurality of first conductive alloy capping layers and the gate line.