Top via stack

An integrated circuit, comprising:

• one or more semiconductor structures, wherein at least one of the one or more semiconductor structures comprises:
• a first metallization layer disposed on a first etch stop layer, wherein the first metallization layer comprises a first conductive line and a second conductive line, each disposed in a first dielectric layer and extending from the first etch stop layer, wherein a height of the first conductive line is greater than a height of the second conductive line;
• a first via layer comprising a second dielectric layer disposed on a top surface of the first metallization layer and a first via and a second via in the second dielectric layer;
• a first conductive material disposed on a top surface of the first conductive line in the first via;
• and
• a second conductive material disposed on a top surface of the second conductive line in the second via.

A method, comprising:

• forming a first metallization layer on a first etch stop layer comprising a first conductive line and a second conductive line in a first dielectric layer;
• selectively recessing a portion of the second conductive line, wherein a height of the first conductive line is greater than a height of the second conductive line;
• depositing a second dielectric layer in the recessed portion of the second conductive line and on a top surface of the first conductive line;
• forming a first via layer comprising a first via in the second dielectric layer and exposing a top surface of the second conductive line;
• and
• depositing a first conductive material in the first via.