Packaged device having selective lead pullback for dimple depth control
AssigneeTexas Instruments Incorporated
InventorRobert F. Mortan
Life of this patent
Estimating the term…
Abstract
A packaged semiconductor device includes a lead frame including plurality of lead terminals each having a plated wettable flank dimple including 2 or more different widths including narrower lead terminals and wider lead terminals. A semiconductor die is attached to the lead frame. A mold material terminates at a saw line of the packaged semiconductor device providing encapsulation except for an exposed bottom contact and an exposed sidewall contact for the plurality of lead terminals. The wider lead terminals have a necked region with a reduced width extending inward a predetermined distance from the saw line, where a terminal region inward beyond the necked region which is wider as compared to the necked region.
Claims22
A packaged semiconductor device, comprising:
- a lead frame including a plurality of lead terminals each having a plated wettable flank dimple including two or more different widths including narrower lead terminals and wider lead terminals;
- a semiconductor die attached to the lead frame;
- a mold material terminating at a saw line on outer edges of the packaged semiconductor device providing encapsulation except for an exposed bottom contact and an exposed sidewall contact for each of the plurality of lead terminals;
- wherein the wider lead terminals have:
- a necked region with a reduced width extending inward a predetermined distance from the saw line, and
- a terminal region inward beyond the necked region which is wider as compared to the necked region.
A packaged semiconductor device, comprising:
- a plurality of lead terminals including narrower lead terminals and wider lead terminals each, of the plurality of lead terminals having a plated flank dimple;
- a semiconductor die spaced from the plurality of lead terminals;
- a mold material terminating at a saw line on outer edges of the packaged semiconductor device providing encapsulation except for an exposed bottom contact and an exposed sidewall contact for each of the plurality of lead terminals;
- wherein the wider lead terminals have:
- a necked region with a reduced width extending inward a predetermined distance from the saw line, and
- a terminal region inward beyond the necked region which is wider as compared to the necked region.
A semiconductor package assembly, comprising:
- a plurality of lead terminals including wider lead terminals and narrower lead terminals;
- a reduced lead width along a length dimension of only the wider lead terminals to a predetermined distance inwards from an outer edge of the wider lead terminals to form necked regions;
- and
- plated wettable flank dimples in the plurality of lead terminals.
A semiconductor package assembly, comprising:
- lead terminals having a first width and lead terminals having a second width, the second width being less that the first width, each lead terminal having a plated wettable flank dimple;
- and
- a neck etching a predetermined distance inwards from an outer edge of the lead terminals having a first width to form necked regions.
Dependencies are inferred from the claim text.