Semiconductor devices including a lower semiconductor package, an upper semiconductor package on the lower semiconductor package, and a connection pattern between the lower semiconductor package and the upper semiconductor package

A semiconductor device, comprising:

• a lower semiconductor package;
• an upper semiconductor package including at least one chip and on the lower semiconductor package;
• and
• a connection pattern between the lower semiconductor package and the upper semiconductor package, and configured to electrically connect the lower semiconductor package and the upper semiconductor package to each other,
• wherein the lower semiconductor package includes:
• a lower base;
• a first lower chip on the lower base;
• and
• a mold layer on the lower base and contacting a side surface of the first lower chip,
• wherein the first lower chip includes:
• a substrate;
• a first insulating layer on the substrate;
• a chip pad on the first insulating layer;
• a pad structure on the first insulating layer and including a first pad and a second pad on the first pad;
• a redistribution line on the first insulating layer and configured to electrically connect the chip pad and the pad structure;
• a heat sink structure on the first insulating layer;
• and
• a second insulating layer on the first insulating layer, contacting a first portion of the chip pad, a portion of the pad structure and a portion of the redistribution line, and covering at least an upper surface of the redistribution line, and
• wherein at least a portion of the heat sink structure is at a same height level as at least a second portion of the pad structure.

A semiconductor device, comprising:

• a lower semiconductor package;
• an upper semiconductor package including at least one chip and on the lower semiconductor package;
• and
• a connection pattern between the lower semiconductor package and the upper semiconductor package, and configured to electrically connect the lower semiconductor package and the upper semiconductor package to each other,
• wherein the lower semiconductor package includes:
• a lower base;
• a first lower chip on the lower base;
• and
• a mold layer on the lower base and contacting a side surface of the first lower chip,
• wherein the first lower chip includes:
• a chip pad;
• a pad structure including a first pad and a second pad on the first pad;
• and
• a redistribution line configured to electrically connect the chip pad and the first pad;
• a heat sink structure,
• wherein the chip pad and the first pad are each at a same height level as the redistribution line,
• wherein at least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure,
• wherein the mold layer includes a portion overlapping a top surface of the redistribution line, and
• wherein the connection pattern contacts the second pad.