Chip package with staggered pin pattern

A microelectronics package comprising:

• a package substrate having a first surface and an opposite second surface;
• one or more integrated circuit chips coupled to the first surface of the package substrate;
• and
• an array of conductive contacts on the second surface of the package substrate, and configured to electrically couple to one or more corresponding conductive contacts on a substrate separate from the microelectronics package, wherein the array of conductive contacts has a staggered two-dimensional arrangement, such that a first column of conductive contacts is separated from a second column of conductive contacts in a first direction by a first distance without an interveing column of conductive contacts between the first column of conductive contacts and the second column of conductive contacts, wherein the second column of conductive contacts are located at different positions in a second direction perpendicular to the first direction from the first column of conductive contacts, and wherein the second column of conductive contacts is separated from a third column of conductive contacts in the first direction by a second distance less than the first distance, wherein the third column of conductive contacts is located at a different position in the second direction from the second column of conductive contacts.