Defect detection structure of a semiconductor die, semiconductor device including the same and method of detecting defects in semiconductor die

A defect detection structure in a peripheral region of a semiconductor die surrounding a central region of the semiconductor die, the defect detection structure comprising:

• a first conduction loop in a left-bottom corner region of the peripheral region;
• a second conduction loop in a right-bottom corner region of the peripheral region;
• a third conduction loop in the left-bottom corner region and a left-upper corner region of the peripheral region;
• and
• a fourth conduction loop in the right-bottom corner region and a right-upper corner region of the peripheral region,
• wherein the first conduction loop and the second conduction loop are formed using a first conduction layer and a second conduction layer, and the third conduction loop and the fourth conduction loop are formed using the first conduction layer and a third conduction layer,
• wherein an input end node of the defect detection structure is configured to receive a test input signal,
• wherein first, second, third, and fourth output end nodes of the first, second, third and fourth conduction loops are configured to output respective first, second, third, and fourth test output signals,
• wherein the first, second, third and fourth conduction loops are connected to the input end node at respective opposite ends of the first, second, third and fourth conduction loops from respective ones of the first, second, third, and fourth output end nodes of the first, second, third and fourth conduction loops.

A defect detection structure in a peripheral region of a semiconductor die surrounding a central region of the semiconductor die, the defect detection structure comprising:

• a first conduction loop in a left-bottom corner region of the peripheral region;
• a second conduction loop in a right-bottom corner region of the peripheral region;
• a third conduction loop in the left-bottom corner region and a left-upper corner region of the peripheral region;
• and
• a fourth conduction loop in the right-bottom corner region and a right-upper corner region of the peripheral region,
• wherein the first conduction loop and the second conduction loop are formed using a first conduction layer, and the third conduction loop and the fourth conduction loop are formed using the first conduction layer and a second conduction layer,
• wherein an input end node of the defect detection structure is configured to receive a test input signal,
• wherein first, second, third, and fourth output end nodes of the first, second, third and fourth conduction loops are configured to output respective first, second, third, and fourth test output signals,
• wherein the first, second, third and fourth conduction loops are connected to the input end node at respective opposite ends of the first, second, third and fourth conduction loops from respective ones of the first, second, third, and fourth output end nodes of the first, second, third and fourth conduction loops.