Nanoscale-aligned three-dimensional stacked integrated circuit

A method for fabricating a three-dimensional (3D) system on a chip (SoC), the method comprising:

• assembling a Layer-(k) two-dimensional (2D)-die array onto a Layer-(k−1) 2D-die array of a Layer-(k−1) wafer, wherein said Layer-(k−1) wafer is populated with 2D-dies, wherein said k is a positive integer number greater than 1, wherein said 2D-die array comprises a single 2D-die, a single island of 2D-die that forms a contiguous group of 2D die or multiple islands of 2D die;
• and
• providing an encapsulation layer for protecting 2D-dies in each of Layer-(k) wafer and said Layer-(k−1) wafer from etchants used during a pick-and-place process.

A method for fabricating a three-dimensional (3D) system on a chip (SoC), the method comprising:

• assembling a Layer-(k) two-dimensional (2D)-die array onto a Layer-(k−1) 2D-die array of a Layer-(k−1) wafer, wherein said Layer-(k−1) wafer is populated with 2D-dies, wherein said k is a positive integer number greater than 1, wherein said 2D-die array comprises a single island of 2D-die that forms a contiguous group of 2D die or multiple islands of 2D die, wherein said 2D-dies have a thickness less than 10 micrometers, wherein said SoC comprises an application specific integrated circuit (ASIC) system, wherein said ASIC system comprises logic and memory circuitry designed and manufactured in three dimensions (3D) using a pick-and-place method, which allows precision overlay of said logic and memory circuitry.

An electronic design automation (EDA) methodology for designing three-dimensional (3D) application specific integrated circuit (ASIC) system on a chip (SoC) logic circuitry comprising:

• a combination of software integrated with two-dimensional (2D) EDA solutions, wherein said software comprises a netlist partitioning algorithm to partition a 3D design netlist into 2D modules, wherein each of said 2D modules comprises logic cells to be placed on different layers of a 3D SoC stack, wherein each of said 2D modules comprises input/output ports placed anywhere in said 2D module, wherein said 2D EDA solutions are used to perform one or more of the following:
• synthesis, 3D placement aware synthesis, placement, clock tree synthesis (CTS), routing, design verification and signoff analysis.