Air gaps in memory array structures

A device comprising:

• a semiconductor substrate;
• a first memory cell over the semiconductor substrate, the first memory cell comprising a first transistor, wherein the first transistor comprises:
• a first gate electrode comprising a portion of a first word line, wherein a bottom surface of the first gate electrode is exposed by a first air gap, wherein a top surface of the first gate electrode is exposed by a second air gap;
• a first portion of a ferroelectric material, wherein the first portion of the ferroelectric material is on a sidewall of the first gate electrode;
• and
• a first channel region on a sidewall of the first portion of the ferroelectric material;
• a source line, wherein a first portion of the source line provides a first source/drain electrode for the first transistor;
• a bit line, wherein a first portion of the bit line provides a second source/drain electrode for the first transistor;
• and
• a first dielectric material separating the source line and the bit line.

A method comprising:

• depositing alternating layers of conductive material and sacrificial material to form a multi-layer stack comprising a plurality of conductive material layers and a plurality of sacrificial material layers;
• depositing a memory film along a sidewall of the multi-layer stack;
• depositing an oxide semiconductor (OS) layer over the memory film;
• forming an inter-metal dielectric layer (IMD) over the multi-layer stack;
• patterning a plurality of trenches in the IMD, wherein each trench of the plurality of trenches exposes a respective sacrificial material layer of the plurality of sacrificial material layers;
• performing an etching process within the plurality of trenches to remove the plurality of sacrificial material layers, wherein removing the plurality of sacrificial layers forms air gaps between conductive material layers of the plurality of conductive material layers;
• depositing a dielectric material in the plurality of trenches, wherein the dielectric material seals the air gaps;
• performing an etching process within the plurality of trenches to extend each trench through the dielectric material and expose a respective conductive material layer;
• and
• depositing a conductive fill material in the plurality of trenches to form a plurality of contacts, wherein each contact physically and electrically contacts a respective conductive material layer.