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US 11,600,519 B2Granted
Skip-via proximity interconnect
AssigneeInternational Business Machines Corporation
InventorsYann Mignot, Hsueh-Chung Chen
Life of this patent
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Abstract
A method of forming vias and skip vias is provided. The method includes forming a blocking layer on an underlying layer, and forming an overlying layer on the blocking layer. The method further includes opening a hole in the overlying layer that overlaps the blocking layer, and etching past the blocking layer into the underlying layer to form a second hole that is smaller than the hole in the overlying layer.
Claims19
A method of forming vias and skip vias comprising:
- forming a plurality of discontinuous conductive blocking layer sections on an underlying layer;
- forming an overlying layer on the plurality of discontinuous conductive blocking layer sections, wherein the overlying layer includes a hardmask capping layer on the discontinuous conductive blocking layer sections, an organic planarization layer on the hardmask capping layer, a silicon anti-reflection coating (MARC) layer on the organic planarization layer, and a resist layer on the SiARC layer;
- opening a first hole in the resist layer that overlaps one of the plurality of discontinuous conductive blocking layer sections;
- etching through the SiARC layer, the organic planarization layer, and the hardmask capping layer, and past the one discontinuous conductive blocking layer section into the underlying layer to form a second hole that is smaller than the first, hole in the overlying layer, wherein the second hole exposes at least a portion of a sidewall of the one discontinuous conductive blocking layer section and a portion of a metallization layer section;
- and
- forming a third hole in the overlying layer and underlying layer that does not intersect the plurality of discontinuous conductive blocking layer sections, wherein the third hole exposes a conductive line below the metallization layer section.
3 more elements
A method of forming vias and skip vias comprising:
- forming a patterned resist layer over a second metallization layer section, a first metallization layer section, and an arrangement of conductive lines on a substrate, wherein the patterned resist layer has at least one resist opening in the patterned resist layer laterally aligned with the second metallization layer section, the first metallization layer section, or the conductive line, wherein the at least one resist opening overlaps an edge of the second metallization layer section or the first metallization layer section;
- extending the at least one resist opening through an intervening fourth organic planarization layer and third capping layer to the second metallization layer section, and to the first metallization layer section or the conductive lines to form one or more trenches for the vias and skip vias;
- and
- filling the one or more trenches with a fourth metallization layer, wherein the fourth metallization layer is in physical and electrical contact with the second metallization layer section, and the first metallization layer section or the conductive line to provide the vias and skip vias.
1 more element
A device, comprising:
- an arrangement of conductive lines on a substrate;
- a first capping layer on the substrate and the arrangement of conductive lines;
- a first dielectric layer on the first capping layer;
- a plurality of first metallization layer sections in the first dielectric layer that are in electrical contact with the arrangement of conductive lines;
- a second capping layer on the plurality of first metallization layer sections;
- a second dielectric layer on the second capping layer;
- a plurality of second metallization layer sections in the second dielectric layer;
- a via between at least one of the plurality of second metallization layer sections and at least one of the plurality of first metallization layer sections;
- and
- one or more skip via(s) to at least one of the arrangement of conductive lines, wherein the plurality of second metallization layer sections define the edges of the vias, so the second dielectric layer does not have chamfering.
7 more elements
Dependencies are inferred from the claim text.