Geometrically configurable planar wafers
AssigneeRockwell Collins, Inc.
InventorsJoshua Gerdes, Jeffrey J. Deloy, James B. Mayfield, Tristan J. Kendall, Steven Stowe
Life of this patent
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Abstract
A system of modular components each include pin ports that may be connected in different configurations to enact alternative planar designs. Each modular component has asymmetries that are utilized to facilitate alternative wiring. Such asymmetries could include protrusions in the wafer to align edge connections. Alternatively, or in addition, the asymmetries include differences in copper disposition to certain edge connections. Each modular component has a non-conductive coating on each side of the wafer to insulate the underlaying copper layer.
Claims13
A printed circuit board wafer comprising:
- a first conductive layer disposed on a first surface;
- a second conductive layer disposed on a second surface;
- a non-conductive core;
- and
- one or more vias connecting the first conductive layer to the second conductive layer through the non-conductive core,
- wherein:
- the wafer defines a center hole configured to receive a transformer core element;
- the wafer defines a plurality of edge connection points, the plurality of edge connection points comprises a plurality of active edge connection points and a plurality of inactive edge connection points;
- at least a first edge connection point is in electronic communication with the first conductive layer but not the second conductive layer;
- at least a second edge connection point is in electronic communication with the second conductive layer but not the first conductive layer;
- and
- the first conductive layer and second conductive layer are asymmetrical at the plurality of edge connection points.
A kit comprising:
- A plurality of printed circuit board wafers, each comprising:
- a first conductive layer disposed on a first surface;
- a second conductive layer disposed on a second surface;
- a non-conductive core;
- and
- one or more vias connecting the first conductive layer to the second conductive layer through the non-conductive core,
- wherein:
- each wafer:
- defines a center hole configured to receive a transformer core element;
- defines a plurality of edge connection points comprising a plurality of active edge connection points and a plurality of inactive edge connection points, where at least a first edge connection point is in electronic communication with the first conductive layer but not the second conductive layer;
- and at least a second edge connection point is in electronic communication with the second conductive layer but not the first conductive layer;
- and
- comprises asymmetrical edge connection points respective to the first conductive layer and the second conductive layer;
- at least one of the wafers comprises a first conductive layer defining a boundary element configured to split the corresponding first conductive layer and direct a current from a connected edge connection point, around the center hole, to at least one of the one or more corresponding vias;
- at least one of the wafers comprises a first conductive layer defining a boundary element configured to split the corresponding first conductive layer and direct a current from a connected edge connection point, around the center hole, to at least one of the one or more corresponding vias and a second conductive layer defining a boundary element configured to split the corresponding second conductive layer and direct a current from the at least one of the one or more vias, around the center hole, to a connected edge connection point.
Dependencies are inferred from the claim text.