Static random-access memory (SRAM) fault handling apparatus and SRAM fault handling method
AssigneeMagnaChip Semiconductor, Ltd.
InventorSangsu Park
Life of this patent
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Abstract
A fault handling apparatus and a fault handling method which perform a built-in self-test (BIST) and a repair on a static random-access memory (SRAM) cell, and the fault handling apparatus and the fault handling method store the fault and repair history information of a previous SRAM test, provide the information to a current test, and reflect both BIST results and the information on the previous test, thereby performing multiple repairs until there is no available spare SRAM.
Claims26
A fault handling apparatus for a static random-access memory (SRAM) including a real memory area and a spare memory area, comprising:
- a memory unit configured to store repair information;
- a command map configured to obtain the repair information of a previous test from the memory unit and provide the repair information of the previous test;
- a built-in self-test (BIST) block unit configured to obtain the repair information of the previous test from the command map, perform a fault test on an entire address of a SRAM cell, distinguishes whether a fault address where a fault has occurred is a real address or a spare address, and store fault address information related to the fault address;
- an update unit configured to update the fault address information by using the repair information of the previous test obtained from the command map and the fault address information obtained from the BIST block unit;
- and
- a remapping control unit configured to update the repair information by remapping the repair information based on the repair information of the previous test and the updated fault address information obtained from the update unit, and transmit the updated repair information to the command map,
- wherein the command map configured to obtain the updated repair information and store in the memory unit.
A method of handling a fault of a static random-access memory (SRAM) including a real memory area and a spare memory area, the method comprising:
- reading repair information of a previous test stored in a memory unit;
- providing the repair information of the previous test to a built-in self-test (BIST) circuit;
- performing a fault test on entire address of an SRAM cell by the BIST circuit;
- when a fault occurs during the fault testing, determining whether the fault has occurred is a real address or a spare address, and storing fault address information related to the fault address;
- updating the fault address information by using the fault address information and the repair information of the previous test;
- updating the repair information based on the updated fault address information and the repair information of the previous test and transmit the updated repair information to a command map;
- and
- storing the updated repair information in the memory unit.
Dependencies are inferred from the claim text.