Memory device capable of repairing defective word lines

A memory device comprising:

• a plurality of word lines grouped into a plurality of word line (WL) sets;
• and
• a plurality of redundant word lines grouped into M redundant word line (RWL) sets;
• a memory control circuit connected to the WL sets and the RWL sets and configured to replace a plurality of defective WL sets of the plurality WL sets by selecting from the RWL sets;
• and
• a plurality of fuse sets, wherein each of the plurality of fuse sets comprise a plurality of fuses used to record the addresses of one of the defective WL sets and to record an availability of the fuse set, wherein
• each of the plurality of defective WL sets comprises at least a defective word line,
• all of the M RWL sets are available for repairing the WL sets during a wafer stage, where M is an integer greater than 2, and
• N of M RWL sets is available for repairing the WL sets during the wafer stage, during a package stage and during a post package stage, where N is an integer less than M,
• wherein the plurality of fuse sets are grouped into a first fuse set group, a second fuse set group, and a third fuse set group, wherein fuse sets of the first fuse set group are used to record addresses of defective WL sets during the wafer stage exclusively, fuse sets of the second fuse set group are used to record addresses of defective WL sets during package stage exclusively, and fuse sets of the third fuse set are used to record group addresses of defective WL sets during post package stage exclusively.