Test method for memory device, operation method of test device testing memory device, and memory device with self-test function
AssigneeSamsung Electronics Co., Ltd.
InventorJung Hyuk Lee
Life of this patent
Estimating the term…
Abstract
A test method for a memory device including a plurality of memory cells includes generating a first test pattern, performing a first pattern write operation of writing the first test pattern in the plurality of memory cells, reading first data from the plurality of memory cells in which the first test pattern was written, generating a second test pattern based on the first data, and performing a second pattern write operation of writing the second test pattern in the plurality of memory cells. The second test pattern is generated such that a write operation is skipped with regard to failure cells from among the plurality of memory cells at which a write failure occurs, during the second pattern write operation.
Claims13
A memory device comprising:
- a memory cell array including a plurality of memory cells;
- a driving circuit configured to perform a write operation and a read operation on the plurality of memory cells;
- a test register configured to temporarily store data read from the plurality of memory cells during a test operation of the memory cell array, and to generate a test pattern by combining the data stored therein and a default test pattern;
- and
- a control logic circuit configured to iteratively perform a write operation on the plurality of memory cells during the test operation using the test pattern.
A method of manufacturing a memory device comprising:
- forming the memory device as part of a wafer including the memory device and at least one other memory device, the memory device including a plurality of memory cells;
- and
- testing the memory device,
- the testing of the memory device comprising iteratively performing a pattern write operation on the plurality of memory cells, and writing failure information in failure memory cells from among the plurality of memory cells at which a write failure occurs.
Dependencies are inferred from the claim text.