Methods of testing nonvolatile memory devices

A method of testing a nonvolatile memory device including a first chip and a second chip, wherein the first chip includes a memory cell region and is provided on a first wafer and the second chip includes a peripheral circuit region having a page buffer circuit and is provided on a second wafer different from the first wafer, the method comprising:

• providing circuit elements including the page buffer circuit by forming semiconductor elements and patterns for wiring the semiconductor elements in a first substrate on the second wafer;
• mimicking an on state of memory cells which are not connected to the page buffer circuit by proving a conducting path between an internal node of a bit-line connection circuit and a voltage terminal to receive a first voltage, bit-line connection circuit being connected between a sensing node and a bit-line node of the page buffer circuit;
• performing, in the page buffer circuit, a sensing and latching operation with the on state being mimicked;
• and
• determining whether the page buffer circuit operates normally based on a result of the sensing and latching operation.

A method of testing a nonvolatile memory device including a memory cell array and a page buffer circuit coupled to the memory cell array through a plurality of bit-lines, wherein the memory cell array includes a plurality of nonvolatile memory cells, the method comprising:

• turning-off a string selection transistor of at least one NAND string with the least one NAND string being connected to the page buffer circuit through at least one bit-line of the plurality of bit-lines;
• providing a conducting path between an internal node of a bit-line connection circuit and a voltage terminal to receive a first voltage, the bit-line connection circuit being connected between a sensing node and a bit-line node of the page buffer circuit, the bit-line node being coupled to the at least one bit-line;
• performing, in the page buffer circuit, a sensing and latching operation;
• and
• determining whether the page buffer circuit operates normally based on a result of the sensing and latching operation.