Storage device
AssigneesKabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
InventorToshiaki Dozaka
Life of this patent
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Abstract
According to an embodiment, a storage device includes a plurality of storage elements, a plurality of readout circuits, and a delay circuit. The readout circuits include a first readout circuit and a second readout circuit different from the first readout circuit. The readout circuits each determines data stored in a corresponding one of the storage elements and outputs a result of the determination, in response to receipt of an activation signal. The delay circuit is connected at a first end to the first readout circuit and connected at a second end to the second readout circuit. The delay circuit supplies the activation signal to the second readout circuit with a time interval after supplying the activation signal to the first readout circuit.
Claims20
A storage device comprising:
- a plurality of storage elements;
- a plurality of readout circuits including a first readout circuit, a second readout circuit different from the first readout circuit, and a third readout circuit different from the first readout circuit and the second readout circuit, the readout circuits each of which determines data stored in a corresponding one of the plurality of storage elements and outputs a result of the determination, in response to receipt of an activation signal;
- a first delay circuit connected at a first end to the first readout circuit and connected at a second end to the second readout circuit, the first delay circuit that supplies the activation signal to the second readout circuit with a time interval according to a delay characteristic of the first delay circuit after supplying the activation signal to the first readout circuit;
- and
- a second delay circuit connected at a third end to the second readout circuit and connected at a fourth end to the third readout circuit, the second delay circuit that supplies the activation signal to the third readout circuit with a time interval according to a delay characteristic of the second delay circuit after supplying the activation signal to the second readout circuit, wherein
- the first readout circuit comprises a first node that makes a state transition in accordance with the data,
- the first delay circuit comprises a sensing circuit that detects completion of the data determination from a state of the first node, and
- the first delay circuit supplies the activation signal to the second readout circuit after the sensing circuit detects the completion of the data determination.
A storage device comprising:
- a plurality of storage elements;
- a plurality of readout circuits including a first readout circuit and a second readout circuit different from the first readout circuit, the readout circuits each of which determines data stored in a corresponding one of the plurality of storage elements and outputs a result of the determination, in response to receipt of an activation signal;
- and
- a delay circuit connected at a first end to the first readout circuit and connected at a second end to the second readout circuit, the delay circuit that supplies the activation signal to the second readout circuit with a time interval after supplying the activation signal to the first readout circuit, wherein
- the delay circuit supplies the activation signal to the second readout circuit after the first readout circuit completes the data determination in response to receipt of the activation signal, wherein
- the first readout circuit comprises a first node that makes a state transition in accordance with the data,
- the delay circuit comprises a sensing circuit that detects completion of the data determination from a state of the first node, and
- the delay circuit supplies the activation signal to the second readout circuit after the sensing circuit detects the completion of the data determination.
Dependencies are inferred from the claim text.