Memory devices with dynamic program verify levels

A memory device comprising:

• an array of memory cells;
• and
• a controller configured to access the array of memory cells to program a selected memory cell of the array of memory cells,
• wherein the controller is further configured to:
• apply a particular program pulse to the selected memory cell;
• sense whether the selected memory cell has been programmed to a first program verify level less than a final program verify level;
• apply a first subsequent program pulse to the selected memory cell;
• sense whether the selected memory cell has been programmed to a second program verify level less than the final program verify level and greater than the first program verify level;
• apply a second subsequent program pulse to the selected memory cell;
• and
• sense whether the selected memory cell has been programmed to the final program verify level.

A memory device comprising:

• an array of memory cells comprising a plurality of strings of series-connected memory cells;
• a plurality of access lines, each access line of the plurality of access lines connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells;
• and
• a controller configured to program each respective memory cell connected to a selected access line of the plurality of access lines to a respective target level,
• wherein the controller is further configured to:
• sense a first threshold voltage of each respective memory cell connected to the selected access line;
• inhibit programming of each respective memory cell connected to the selected access line in response to the sensed first threshold voltage of the respective memory cell being greater than a first program verify level for the respective memory cell, wherein the first program verify level for the respective memory cell is less than a final program verify level for the respective memory cell;
• enable programming of each respective memory cell connected to the selected access line in response to the sensed first threshold voltage of the respective memory cell being less than the first program verify level for the respective memory cell;
• apply a particular program pulse to the selected access line;
• sense a second threshold voltage of each respective memory cell connected to the selected access line;
• inhibit programming of each respective memory cell connected to the selected access line in response to the sensed second threshold voltage of the respective memory cell being greater than the final program verify level for the respective memory cell;
• enable programming of each respective memory cell connected to the selected access line in response to the sensed second threshold voltage of the respective memory cell being less than the final program verify level for the respective memory cell;
• and
• apply a first subsequent program pulse to the selected access line.