Method for reading three-dimensional flash memory
AssigneeYangtze Memory Technologies Co., Ltd.
InventorsZilong Chen, Xiang Fu
Life of this patent
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Abstract
A method for conducting a read-verification operation on a target memory cell in a three-dimensional (3D) memory device includes removing fast charges of the target memory cell at a read-prepare step and measuring a threshold voltage of the target memory cell at a sensing step. Removing the fast charges of the target memory cell includes applying a prepare voltage (Vprepare) on an unselected top select gate (Unsel_TSG) of an unselected memory string, applying a first off voltage (Voff) on a selected word line (Sel_WL) associated with the target memory cell, and applying a pass voltage (Vpass) on an unselected word line (Unsel_WL).
Claims20
A method for conducting a read-verification operation on a target memory cell in a three-dimensional (3D) memory device, comprising:
- applying, on an unselected top select gate of an unselected memory string, a prepare voltage during a first time period and an off voltage during a second time period;
- applying, on a selected word line associated with the target memory cell, the off voltage during the first time period and a read voltage during the second time period;
- and
- applying, on an unselected word line, a pass voltage during the first time period and the second time period,
- wherein the read-verification operation removes fast charges of the target memory cell during the first time period.
A three-dimensional (3D) memory device, comprising:
- a memory array, comprising a plurality of memory strings extending vertically through a film stack of alternating conductive and dielectric layers, wherein:
- each memory string comprises a plurality of memory cells;
- and
- each memory cell is addressable through a word line and a bit line;
- and
- a circuit of the memory array configured to conduct, on a target memory cell, a read-verification operation for removing fast charges during a first time period, wherein the circuit is configured to:
- apply, on an unselected top select gate of an unselected memory string, a prepare voltage during the first time period and an off voltage during a second time period;
- apply, on a selected word line associated with the target memory cell, the off voltage during the first time period and a read voltage during the second time period;
- and
- apply, on an unselected word line, a pass voltage during the first time period and the second time period.
Dependencies are inferred from the claim text.