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US 11,600,337 B2Granted
Memory device read operations
AssigneeMicron Technology, Inc.
InventorYoshihiko Kamata
Life of this patent
Estimating the term…
Abstract
Memory devices might include a capacitor, a first capacitance element, a first transistor, and control logic. The first transistor might be connected between the capacitor and the first capacitance element. The control logic might be connected to a control gate of the first transistor. The control logic might be configured to activate the first transistor to precharge the capacitor and the first capacitance element during a read operation of the memory device. The first capacitance element might be a wire capacitance of a first signal line.
Claims38
A memory device comprising:
- a capacitor;
- a first capacitance element;
- a first transistor connected between the capacitor and the first capacitance element;
- a second capacitance element;
- and
- a second transistor connected between the first capacitance element and the second capacitance element;
- and
- control logic connected to a control gate of the first transistor and to a control gate of the second transistor, the control logic configured to activate the first transistor and the second transistor to precharge the capacitor, the first capacitance element, and the second capacitance element during a read operation of the memory device.
5 more elements
A memory device comprising:
- a string of series-connected memory cells;
- a data line selectively connected to the string of series-connected memory cells;
- a sense capacitor selectively connected to the data line;
- a first capacitance element selectively connected to the sense capacitor;
- and
- control logic configured to:
- electrically connect the sense capacitor and the first capacitance element to each other;
- discharge the sense capacitor and the first capacitance element to a first voltage;
- precharge the data line to a second voltage;
- with the sense capacitor and the first capacitance element discharged to the first voltage and with the data line precharged to the second voltage, temporarily electrically connect the sense capacitor and the first capacitance element to the data line;
- and
- with the sense capacitor and the first capacitance element disconnected from the data line, sense a state of a selected memory cell of the string of series-connected memory cells based on a voltage on the sense capacitor and the first capacitance element.
9 more elements
A memory device comprising:
- a string of series-connected memory cells;
- a data line selectively connected to the string of series-connected memory cells;
- a page buffer connected to the data line, wherein the page buffer comprises:
- a sense transistor comprising a gate, a drain, and a source, the gate and the drain selectively connected to the data line;
- and
- a first multiplexer comprising an output connected to the drain of the sense transistor, a first input connected to a first bias node, and a second input connected to a second bias node.
3 more elements
A memory device comprising:
- an array of memory cells comprising a plurality of strings of series-connected memory cells;
- a plurality of data lines, wherein each string of series-connected memory cells of the plurality of strings of series-connected memory cells is selectively electrically connected to a respective data line of the plurality of data lines;
- and
- a page buffer connected to the plurality of data lines, wherein for each data line of the plurality of data lines the page buffer comprises:
- a sense transistor comprising a gate and a drain selectively connected to the data line;
- a first multiplexer comprising an output connected to a drain of the sense transistor, a first input connected to a first bias node, and a second input connected to a second bias node configured to receive a reference voltage;
- and
- a voltage regulator to apply a regulated voltage to the first bias node based on a selected one of a plurality of input voltages to the voltage regulator.
5 more elements
A page buffer for a memory device, the page buffer comprising:
- a sense capacitor;
- a first signal line comprising a first wire capacitance;
- a second signal line comprising a second wire capacitance;
- a first transistor connected between the sense capacitor and the first signal line;
- a second transistor connected between the first signal line and the second signal line;
- a sense transistor comprising a gate, a drain, and a source, the gate connected to the sense capacitor and the drain selectively connected to the first signal line;
- and
- a first multiplexer comprising an output connected to the drain of the sense transistor, a first input connected to a first bias node, and a second input connected to a second bias node.
5 more elements
Dependencies are inferred from the claim text.