Page buffer circuits and nonvolatile memory devices including the same

A nonvolatile memory device comprising:

• a first semiconductor layer including a plurality of memory cells connected to each of a plurality of bit-lines extending in a first horizontal direction;
• and
• a second semiconductor layer in a vertical direction to the first semiconductor layer and including a page buffer circuit,
• wherein the page buffer circuit includes:
• a main region including a plurality of page buffer units in the first horizontal direction;
• and
• a cache region adjacent to the main region in the first horizontal direction, the cache region including a plurality of cache latches in the first horizontal direction and commonly connected to a combined sensing node, the plurality of cache latches corresponding to respective ones of the plurality of page buffer units,
• wherein each of the plurality of page buffer units includes a pass transistor connected to each sensing node and driven based on a pass control signal, and
• wherein while performing a first data output operation to output data, the data used in the first data output operation having been provided from a first portion of page buffer units among the plurality of page buffer units, from a first portion of cache latches among the plurality of cache latches to a data input/output (I/O) line, the page buffer circuit is configured to perform a data transfer operation to dump sensed data from a second portion of page buffer units among the plurality of page buffer units to a second portion of cache latches among the plurality of cache latches, the page buffer circuit configured to output the data from the first portion of cache latches while dumping the sensed data from the second portion of page buffer units to the second portion of cache latches.

A page buffer circuit comprising:

• a plurality of page buffer units;
• and
• a plurality of cache latches commonly connected to the plurality of page buffer units via a combined sensing node, the plurality of cache latches corresponding to respective ones of the plurality of page buffer units,
• wherein each of the plurality of page buffer units includes a pair of pass transistors and a sensing node to connect the pair of pass transistors to each other, and
• in a data transfer period, between the plurality of page buffer units and the plurality of cache latches, sensing node lines included in each of the plurality of page buffer units are connected to the combined sensing node, and the plurality of page buffer units are electrically connected to the plurality of cache latches, and
• wherein while the page buffer circuit performs a first data output operation to output data, the data used in the first data output operation having been provided from a first portion of page buffer units among the plurality of page buffer units, from a first portion of cache latches among the plurality of cache latches to a data input/output (I/O) line, the page buffer circuit is configured to perform a data transfer operation to dump sensed data from a second portion of page buffer units among the plurality of page buffer units to a second portion of cache latches among the plurality of cache latches, the page buffer circuit configured to output the data from the first portion of cache latches while dumping the sensed data from the second portion of page buffer units to the second portion of cache latches.