US 11,600,334 B2 · Memory controller

Abstract

In a memory controller for controlling a memory device including a memory block coupled to a plurality of word lines, the memory block including a plurality of memory cells respectively coupled to the plurality of word lines, the memory controller comprising: an operating time calculator configured to calculate program operating times taken to perform a program operation on the memory cells respectively coupled to the plurality of word lines; and an operating voltage determiner configured to determine an erase voltage to be used to erase a memory block by comparing a first program operating time, among the program operating times calculated by the operating time calculator, with the other program operating times, except the first program operating time, among the program operating times.

Claims11

Dependent claims

A memory controller for controlling a memory device, the memory controller comprising:

a processor configured to obtain an operating time of a first program operation performed on a word line, and obtain an average operating time of second program operations performed on at least two word lines different from the word line after the first program operation among a plurality of word lines coupled to a memory block included in the memory device;
an operating time storage configured to store the operating time as a reference operating time, and store the average operating time;
and
an operating voltage controller configured to, based on a difference between the average operating time and the reference operating time, determine a level of an erase voltage to be applied to the memory block during an erase operation.

1 more element

Dependencies are inferred from the claim text.

Memory controller

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Memory controller

Life of this patent

Abstract

Claims11