Memory device with improved program performance and method of operating the same

A method of operating a memory device including a memory cell array including a plurality of cell strings including a plurality of memory cells connected to a plurality of word lines and a plurality of string selection lines respectively, the plurality of word lines and the plurality of string selection lines vertically stacked on a substrate, the method comprising:

• applying a first voltage to a first word line and a second word line adjacent to the first word line, among the plurality of word lines, and performing a precharge on one or more non-selection cell strings among the plurality of cell strings;
• increasing a voltage applied to a non-selection string selection line among the plurality of string selection lines during the precharge;
• performing a first program operation on memory cells connected to the first word line and the second word line;
• applying a second voltage having a level different from that of the first voltage to the first word line and the second word line;
• performing the precharge on the one or more non-selection cell strings;
• and
• increasing a voltage applied to a selection bit line during the precharge on the one or more non-selection cell strings.

A memory device comprising:

• a memory cell array including a plurality of cell strings including a plurality of memory cells stacked on a substrate in a vertical direction, a plurality of word lines respectively connected to the plurality of memory cells, a plurality of bit lines connected to one side of the plurality of cell strings, and one or more common source lines connected to other side of the plurality of cell strings, the plurality of memory cells including a ground selection transistor connected to a ground selection line, a string selection transistor connected to a string selection line;
• a control logic including a precharge control circuit for controlling precharge on at least one cell string among the plurality of cell strings and controlling a plurality of data program steps on the plurality of memory cells;
• and
• a row decoder for activating at least some of the plurality of word lines in response to a control of the control logic,
• wherein the precharge control circuit controls the row decoder so that, during the precharge on the at least one cell string, a turn-on voltage is applied to a selection word line and a word line adjacent to the selection word line, among the plurality of word lines, a voltage lower than the turn-on voltage is applied to a non-selection word line among the plurality of word lines, a precharge voltage is applied to at least one bit line among the plurality of bit lines, a level of a voltage applied to the ground selection line is increased and a level of a voltage applied to the string selection line.